Active solid-state devices (e.g. – transistors – solid-state diode – Heterojunction device – Bipolar transistor
Reexamination Certificate
1999-04-14
2001-09-04
Fourson, George (Department: 2823)
Active solid-state devices (e.g., transistors, solid-state diode
Heterojunction device
Bipolar transistor
C257S586000
Reexamination Certificate
active
06285044
ABSTRACT:
FIELD OF THE INVENTION
The invention relates generally to semiconductor transistors. In particular, the invention relates to heterojunction bipolar transistors.
BACKGROUND ART
Heterojunction bipolar transistors (HBTs) offer much higher speed of operation than the more prevalent metal-oxide-semiconductor field-effect transistors (MOSFETs) or even conventional homojunction bipolar transistors, e.g., npn or pnp silicon transistors. In some applications where a high degree of linearity is required, HBTs are the alternative technologies of metal semiconductor field effect transistors (MESFETs) and high electron mobility transistors (HEMTs). The use of different materials of differing bandgaps for the collector, base, and emitter provides design flexibility.
The most common HBT technology is based on the GaAs/GaAlAs material family, several features of which are explained by Asbeck in
High
-
Speed Semiconductor Devices,
ed. Sze (Wiley, 1990), pp. 335-338, 358-366, and 370-384.
Asbeck describes one such GaAs HBT, ibid., p. 376, as shown in the cross-sectional view of FIG.
1
. Over a semi-insulating GaAs substrate
10
is formed an n
+
-type collector contact layer
12
, to which a collector contact C is applied. An n
−
-type collector layer
14
and a p
+
-type base layer
16
of GaAs or GaAlAs is grown thereover. A small n
−
-type emitter
18
is formed over the base layer
16
. An emitter contact E is applied to the emitter
18
, and a ring or multiple base contacts B are applied to the base layer
16
.
A disadvantage of the structure described thus far is that the active area is determined by the area of the emitter
18
, but the parasitic capacitance is largely determined by the much larger area of the interface between the base and collector layers
16
,
14
. One method for reducing the base-collector capacitance implants protons into an annular area
20
of the collector layer
14
surrounding the emitter
18
so as to render the implanted area
20
electrically insulating. Asbeck reported a reduction of the capacitance by a factor of two by using proton implantation.
Another HBT technology is based on the InP/InGaAs material family, as is explained by Asbeck, ibid., pp. 384-388. HBTs composed of this material family offer higher speed and can be integrated with opto-electronic devices that are sensitive in the 1.3 and 1.5 &mgr;m optical bands, which have become so important for fiber optic communications. However, InP-based heterojunction bipolar transistors similarly suffer from high base-collector capacitance, and proton implantation has proved ineffective in rendering InP to be insulating or semi-insulating.
Miyamoto et al. have addressed this problem in InP-based HBTs in “Reduction of Base-Collector Capacitance by Undercutting the Collector and Subcollector in GaInAsInP DHBT's,”
IEEE Electron Device Letters
, vol. 17, March 1996, pp. 97-99. By use of a selective etchant, they substantially etched the collector layer under the base layer so as to undercut the edges of the base layer. To provide some mechanical integrity, they then backfilled with polyimide. The reduced size of the collector, together with the lower dielectric constant of the polyimide, reduced the base-collector capacitance. They also reported a reduction of capacitance by about a factor of two. However, the robustness of this structure remains in question.
SUMMARY OF THE INVENTION
Accordingly, an object of the invention is to provide a heterojunction bipolar transistor that exhibits a lower base-collector capacitance.
It is a further object of the invention to provide such a transistor based on the InP/InGaAs family of materials.
An accompanying object of the invention is to provide a method of making such a transistor.
The invention can be summarized as a bipolar transistor, particularly an InP-based heterojunction bipolar transistor and its method of making in which the collector epitaxially grown on the substrate is initially laterally defined and then insulating material, e.g. Fe-doped InP, is regrown around its edges to produce a planar surface on the top of the collector and the insulating material. The thin base layer and the emitter layer are then sequentially epitaxially deposited over the defined collector and its surrounding insulating material. The base and emitter layer are laterally defined over the collector to form both a bipolar transistor stack and contacts extending to respective sides of the base and emitter.
REFERENCES:
patent: 4954457 (1990-09-01), Jambotkar
patent: 5087580 (1992-02-01), Eklund
patent: 5620907 (1997-04-01), Jalali-Farahani et al.
patent: 5736417 (1998-04-01), Oki et al.
patent: 5739062 (1998-04-01), Yoshida et al.
Asbeck, High-Speed Semiconductor Devices, ed. Sze (Wiley, 1990), pp. 335-338, 358-366, and 370-388.
Miyamoto et al., “Reduction of Base-Collector Capacitance by Undercutting the Collector and Subcollector in GaInAsInP DHBT's”IEEE Electron Device Letters, vol. 17, Mar. 1996, pp. 97-99.
Swaminathan et al,Materials Aspects pf GaAs and InP Based Materials: InP, InAs, GaAs, GaP, InGaAs, and InGaAsP, (Prentice Hall, 1991), pp. 116-131, 175-177.
Fourson George
Giordano Joseph
Telcordia Technologies Inc.
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