Innovated AC kicker for high speed low voltage swing...

Details Innovated AC kicker for high speed low voltage swing... Innovated AC kicker for high speed low voltage swing...

1999-07-01

2001-06-12

Lee, Dinh T. (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Current driver

C327S108000, C327S437000, C326S068000

Reexamination Certificate

active

06246270

ABSTRACT:

TECHNICAL FIELD
The present invention relates to output drivers for programmable logic devices (PLDs) or other integrated circuit (IC) outputs. In particular, the present invention is directed to a current kicker or booster circuit to provide for high speed, low voltage output swing for PLD output drivers.
BACKGROUND ART
Programmable logic devices (PLDs) or other types of integrated circuits (ICs) typically use differential output drivers or buffers to drive their outputs. Output drivers are generally driven from inputs provided internally in the IC.
FIG. 1
is a schematic diagram of a differential output buffer or driver
10
which could be used in a PLD or other IC. Driver
10
includes a first input
12
, a second input
14
, a current source
16
, differential amplifier
18
, and first and second outputs
20
and
22
, respectively.
FIG. 1
also shows a typical equivalent load circuit
24
which driver
10
would drive.
Differential amplifier
18
includes first and second transistors
28
and
30
, respectively, the gates of which are controlled by input line
12
and third and fourth transistors
32
and
34
, respectively, the gates of which are controlled by input line
14
. Transistors
28
-
34
are typically all sized approximately the same. The drains of first and fourth transistors
28
and
34
are connected to supply voltages
26
a
and
26
b
, respectively. The source of first transistor
28
is connected to the drain of third transistor
32
and to output
22
. The source of fourth transistor
34
is connected to the drain of second transistor
30
and to output
20
. The sources of second and third transistors
30
and
32
, respectively, are connected to current source
16
. Current source
16
provides a stiff current to drive load
24
and can be a current mirror, the configuration of which is well known in the art.
Equivalent load
24
typically includes a resistance
40
in parallel with a parasitic capacitance
42
across outputs
22
and
24
. Additionally, output
20
is grounded through parasitic capacitance
44
and output
22
is grounded through parasitic capacitance
46
. The values of resistance
40
and capacitances
42
-
46
will vary depending somewhat upon the actual load being driven by driver
10
. However, typically resistance
40
can have a value of about 100 ohms and capacitances
42
,
44
and
46
can each have a value of about 10 picofarads (pf).
Inputs
12
and
14
are driven to either a digital high state (high) or digital low state (low) by the internal electronics of the PLD or other IC. Configuration of PLDs to drive output driver
10
are well known in the art. When first input
12
is high and second input
14
is low, first and second transistors
28
and
30
, respectively, are turned on and third and fourth transistors
32
and
34
, respectively, are turned off. Thus, current can pass from voltage supply
26
a
, through first transistor
28
, into second output
22
, through load
24
and second transistor
30
, and into current source
16
. This drives second output
22
to high and first output
20
low. When first input
12
goes low and second input
14
goes high, third and fourth transistors
32
and
34
, respectively, are turned on and first and second transistors
28
and
30
, respectively, are turned off. Thus, current passes from voltage source
26
b
into first output
20
, through load
24
and to current source
16
through second output
22
. In this way, first output
20
is driven high and second output
22
is driven low.
Typically, outputs
20
and
22
are held at a quiescent dc voltage of about 1.25 volts (v). The voltage swings on outputs
20
and
22
are generally from about 0.25 to 0.45 v between a high state and a low state That is, a high state can be from about 1.5 volts to 1.7 volts and a low state can be from about 0.8 to 1.0 volts.
As noted above, industry specifications generally require an output rise/fall time or slew rate of from 0.3 to 0.5 ns. However, this slew rate can be difficult to achieve given the electrical characteristics of equivalent load
24
. Specifically, it can be difficult for current source
16
to provide a stiff enough current to drive relatively low resistance
40
and parasitic capacitances
42
-
46
to achieve such rapid slew rates.
Accordingly, improvement is needed in output drivers for PLDs or other ICs. Specifically, an output driver should be able to drive a capacitive or low impedance load with a relatively high slew rate to achieve industry standards.
SUMMARY OF THE INVENTION
The present invention includes a current booster for use with an integrated circuit output driver. The output driver has at least one output driven by a primary current source. The current booster includes an auxiliary voltage supply which can be connected to the output of the output driver. The current booster also includes a control mechanism which temporarily connects the auxiliary voltage supply to the output during a change in output state of the output driver.
Preferably, the control mechanism connects the auxiliary voltage supply to the output at the start of a change in state of the output and disconnects the auxiliary voltage supply from the output after the completion of the change in state.
In another aspect of the present invention, a method of boosting the current on an output of an integrated circuit output driver having a first input from an integrated circuit and a primary current source to drive a first output, includes detecting a change in the digital state on the first input from the integrated circuit. An auxiliary voltage supply is then connected to the first output to boost the current of the first output during a change in state thereof.
By boosting the current in the output of a integrated circuit output driver during a change in state thereof, the output driver can advantageously drive a relatively high capacitance, or otherwise low impedance, load relatively quickly. Specifically, industry standard specifications for slew rate can be met even when driving relatively high capacitance loads.


REFERENCES:
patent: 4362955 (1982-12-01), Davenport
patent: 5406139 (1995-04-01), Sharpe-Geisler

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