Semiconductor device manufacturing: process – Packaging or treatment of packaged semiconductor – Metallic housing or support
Reexamination Certificate
2000-03-07
2002-04-23
Bowers, Charles (Department: 2813)
Semiconductor device manufacturing: process
Packaging or treatment of packaged semiconductor
Metallic housing or support
C438S121000, C438S124000
Reexamination Certificate
active
06376282
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to semiconductor device packages. More particularly, the present invention relates to inner-digitized bond fingers on bus bars of lead frames in semiconductor device packages.
2. State of the Art
The advancement of microprocessing technology has resulted in decreases in the physical dimensions of semiconductor devices such as integrated circuit dies or chips. Such dimensional decreases require coresponding decreases in the dimensions of semiconductor device packages, including a reduction in the size of lead frames and leads used in such packages.
In many semiconductor devices, a lead called a “bus bar” is used to distribute operating voltages to several contact areas on the semiconductor device, and to provide a ground bus to individual contact areas. For example, a bus bar can serve as an inner lead for providing a power supply voltage (Vcc) and a reference voltage (Vss) or a ground to the semiconductor chip. The bus bar can be connected to any point on the chip by short distance wire bonding to supply a voltage. This allows the bus bar to be effectively employed to reduce noise and increase processing speed.
Semiconductor device packages having a lead-on-chip structure have been developed to meet the demand that packaging for chips be smaller and thinner. A bus bar is used in a lead-on-chip structure to accommodate a number of wires in a limited space, and the bus bar is positioned on the chip.
A packaged semiconductor device is disclosed in U.S. Pat. No. 5,229,329 to Chai et al., in which a lead-on-chip lead frame having a first array and a second array of opposing lead fingers is utilized in the device. A pair of power supply bus bars lies between the opposing lead fingers, with an insulator covering the face of the bus bars.
In another lead-on-chip semiconductor device disclosed in U.S. Pat. No. 5,532,189 to Kiyono, recessed bus bar regions are provided in an elongated bus bar to accommodate location of bonding wires which couple the chip pads and associated inner leads. Fillets are formed of insulative adhesive material up about the bus bar region sides to thereby engage the bonding wires to prevent contact between the wires and the bus bar.
In conventional lead-on-chip semiconductor device packages with a bus bar, the bonding wires attached to leads and the chip are required to jump over the bus bar, resulting in a relatively higher wire loop and longer wire. Adjacent bonding wires attached to the bus bar and the chip have a relatively shorter wire loop height and length. Thus, the respective bonding wires attached to the bus bars and to the leads have different loop heights and lengths, resulting in more complexity in manufacturing the device.
In U.S. Pat. No. 5,592,020 to Nakao et al., a conventional semiconductor device package (not lead-on-chip) is disclosed in which a chip is mounted on a bed of a lead frame, and leads such as a pair of bus bars have alternating offset projections off the chip. In one embodiment, an elongated portion of one of the bus bars, excluding the projections on the bus bar, is pushed downward away from bonding wires attached to the chip. While the alternating offset projections on the bus bars provide for more uniformity in wire length in this conventional package, the wire lengths are still relatively longer, since the bus bars have to be spread out off the chip to form the offset projections, thereby reducing the speed of the chip.
Accordingly, there is a need for improved bus bar structures that overcome or avoid the above problems in semiconductor devices.
SUMMARY OF THE INVENTION
The present invention is directed to a semiconductor device package such as a lead-over-chip (LOC) integrated circuit package in which at least one pair of bus bar structures on a lead frame in the device has inner-digitized bond fingers for wire bonding to a semiconductor die or chip. The inner-digitized bond fingers provide for substantial uniformity in wire loop height and length for bond wires attached to the bus bars and the chip. This allows for easier manufacture and inspection of an LOC semiconductor device.
In one aspect of the invention, a semiconductor device package includes a lead frame with a plurality of lead members positioned in an array on a first plane along a vertical axis of the lead frame and a semiconductor die secured to the lead frame. At least one pair of bus bars is connected to the lead frame and positioned over the semiconductor die, with a portion of the bus bars positioned over the semiconductor die including a plurality of inner-digitized bond fingers. The inner-digitized bond fingers are formed from a series of alternating projections and recesses on each bus bar. A first plurality of connection members such as bond wires electrically couples the lead members to the semiconductor die. A second plurality of connection members electrically couples the inner-digitized bond fingers of the bus bars to the semiconductor die. The second plurality of connection members preferably has a substantially uniform loop height and length.
An encapsulating material is formed around the semiconductor die, the bus bars, the connection members, and an inner portion of the lead frame to provide a protective covering for the semiconductor device. The portions of the bus bars over the semiconductor die can be offset along the vertical axis from an outer surface of the semiconductor die, or the portions of the bus bars over the semiconductor die can be adjoined to the outer surface of the semiconductor die.
In one preferred embodiment, a semiconductor device package according to the present invention having a lead-over-chip structure includes a lead frame with a plurality of lead fingers positioned in an array. A semiconductor die is secured to the lead frame, with the semiconductor die including first and second pluralities of bond pads. A first bus bar operatively connected to the lead frame traverses over the semiconductor die and includes a plurality of alternating projections and recesses. A second bus bar operatively connected to the lead frame traverses over the semiconductor die adjacent the first bus bar, with the second bus bar also including a plurality of alternating projections and recesses. Each of the projections of the second bus bar extends into a corresponding one of the recesses of the first bus bar, while each of the projections of the first bus bar extends into a corresponding one of the recesses of the second bus bar, thereby forming inner-digitized bond fingers. A first plurality of bond wires electrically couples the first bus bar to the semiconductor die, with each of the first plurality of bond wires being connected to one of the projections of the first bus bar and one of the first plurality of bond pads on the semiconductor die. A second plurality of bond wires electrically couples the second bus bar to the semiconductor die, with each of the second plurality of bond wires traversing the first bus bar to be connected to one of the projections of the second bus bar and one of the second plurality of bond pads on the semiconductor die.
The present invention provides many advantages and benefits in forming a semiconductor device package. The inner-digitized bond fingers on the bus bars in the present invention result in a reduced number of wire groups having different looping parameters, since there is consistency in the wire trajectory and loop height and length of bond wires attached to the bus bars over the die. This allows the wire bonding program to be simpler with respect to set-up and operation, allows line production to run smoother, and provides increased performance to the chip. In addition, production line yield at the wire bond is improved because the bonding target zones on the inner-digitized bond fingers are all at a similar distance from the bond pads. The present invention also provides improved production line yield during encapsulation of a semiconductor device.
In another aspect of the invention, a method for fabricating a
Bowers Charles
Micro)n Technology, Inc.
Smoot Stephen W.
Traskbritt
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