Inline and “Y” input-output bus topology

Details Inline and “Y” input-output bus topology Inline and “Y” input-output bus topology

2001-08-22

2003-12-30

Talbott, David L. (Department: 2827)

Electricity: conductors and insulators

Conduits, cables or conductors

Preformed panel circuit arrangement

C174S260000

Reexamination Certificate

active

06670558

ABSTRACT:

FIELD
The present invention is directed to circuit boards, and more particularly, bus topologies for circuit boards.
BACKGROUND
With increasing processor clock rates in the personal computer, workstation, and server industry, there is a pressing need to provide high speed, economical bus topologies. In particular, designing for high speed and economical communication among more than one processor or agent connected to a bus presents various challenges.
Over the years, many bus topologies have been designed. For example,
FIG. 1
illustrates a “3D” topology (e.g., vertical cards on a motherboard give the interconnect a 3D nature) in which processor modules
102
, along with their associated heat sinks
104
, are mounted on processor cards
106
, which are connected together to chip set
108
via bus
109
on motherboard
110
. (In an actual embodiment, bus
109
and other traces indicated in
FIG. 1
may not be visible.) The connections between an agent, such as a microprocessor, and a bus are often referred to as stubs, and are indicated by numeral
112
in FIG.
1
. For some applications, the stub lengths for the 3D topology of
FIG. 1
are too long, resulting in undesirable signal reflections.
Yet another bus topology is illustrated in
FIG. 2
, sometimes called a “2.5D” topology (because there is less vertical dimension when compared to the 3D topology of FIG.
1
). For this topology, components (processors or agents)
202
, along with their associated heat sinks
204
, are mounted on both sides of motherboard
206
, facing each other, using connectors
210
, and are connected to chip set
208
via bus
209
. A stub is identified by numeral
212
, but not all stubs are shown. Such topologies are relatively expensive due to motherboard assembly costs. Also, for the topology of
FIG. 2
, some of the stubs may be too close to each other, so that signal reflections pose a more serious problem.
Busses with many traces may also present design challenges. Some prior art bus topologies use many layers in the motherboard to route the bus traces to chip packages. However, this adds to motherboard complexity and cost. Alternatively, some prior art bus topologies route the bus traces on only one layer or a few layers of the motherboard. But because the dimension of the chip package is often smaller than the physical width occupied by the bus traces when deposited on one layer, some of the stubs may be too long for some applications.
Embodiments of the present invention are directed to addressing these problems.


REFERENCES:
patent: 3568129 (1971-03-01), Gold
patent: 3628095 (1971-12-01), Schwartz
patent: 4298770 (1981-11-01), Nishihara et al.
patent: 4362899 (1982-12-01), Borrill
patent: 4434321 (1984-02-01), Betts
patent: 5128832 (1992-07-01), Lawrence
patent: 5424490 (1995-06-01), Dombrowski et al.
patent: 5473119 (1995-12-01), Rosenmayer et al.
patent: 5483421 (1996-01-01), Gedney et al.
patent: 5519176 (1996-05-01), Goodman et al.
patent: 5706178 (1998-01-01), Barrow
patent: 5870289 (1999-02-01), Tokuda et al.
patent: 5886876 (1999-03-01), Yamaguchi
patent: 5909010 (1999-06-01), Inoue
patent: 6031728 (2000-02-01), Bedos et al.
patent: 6239387 (2001-05-01), Wissell
patent: 6265673 (2001-07-01), Higashida et al.
patent: 6303871 (2001-10-01), Zu et al.
patent: 6329610 (2001-12-01), Takubo et al.

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