Initializing circuit for MOS integrated circuits

Details Initializing circuit for MOS integrated circuits Initializing circuit for MOS integrated circuits

1979-08-27

1981-10-20

Anagnos, Larry N.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

3072383, 307279, 307594, H03K 17284, H03K 1722, H03K 1716, H03K 508

Patent

active

042963400

ABSTRACT:
An initializing circuit and protection circuit for MOS integrated circuits which employ substrate biasing are disclosed. In one embodiment, a weak depletion mode transistor is coupled between a line in the integrated circuit and ground. The gate of this transistor receives the substrate biasing potential. Since this transistor is enabled without power applied to the circuit, when the circuit is powered-up, this transistor effectively shorts-out the line and prevents the transmission of stray signals. When the substrate biasing potential is reached, the transistor is disabled and effectively removed from the circuit. Once this occurs, normal transmissions on the line are possible.

REFERENCES:
patent: 3753011 (1973-08-01), Faggin
patent: 3895239 (1975-07-01), Alaspa
patent: 3950654 (1976-04-01), Broedner et al.
patent: 3983420 (1976-09-01), Kikuchi
patent: 4013902 (1977-03-01), Payne
patent: 4085458 (1978-04-01), Ikuzaki et al.
patent: 4103187 (1978-07-01), Imamura
patent: 4208595 (1980-06-01), Gladstein et al.
patent: 4210829 (1980-07-01), Wong et al.

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