Initialization setting circuit and semiconductor memory device u

Details Initialization setting circuit and semiconductor memory device u Initialization setting circuit and semiconductor memory device u

1992-04-02

1994-04-26

Fears, Terrell W.

Static information storage and retrieval

Addressing

Including particular address buffer or latch circuit...

36518901, 36518905, G11C 1300

Patent

active

053073193

DESCRIPTION:

BRIEF SUMMARY
FIELD OF THE INVENTION

The present invention relates to a circuit for setting an initial condition of a latch circuit for holding operational conditions of respective circuits in a semiconductor device upon ON-set of power supply, and more particularly, to an improvement for an initialization setting circuit for setting initial conditions of a latch circuit that holds information, such as addresses, control signals, data and so forth in a semiconductor memory device, upon ON-set of power supply.
A latch circuit is provided in a semiconductor memory device, for example, for latching operational conditions of respective circuit. An initialization setting circuit is typically connected to the latch circuit for setting initial condition upon ON-set of the power supply.


BACKGROUND ART

In the conventional semiconductor memory device, as in the construction shown in FIG. 1, for example, an external address signal Add is input to a row decoder 8 and a column decoder 9 as respective row address signal AD1 and column address signal AD2, through an address register 7. Respective decoders produce decode signals based on respective address signals to select a memory cell of the corresponding address in a memory cell array 1, and writing and reading of data is performed.
In this case, the address register 7 receives an activation signal CS from a chip activation register 4 to control the transmission of the address signal ADD for the internal circuit. The activation signal CS is generated, when reference is made to the construction in FIG. 3, by a chip activation register on the basis of a chip selection signal CSX of an active row, the chip selection signal of which is supplied externally. In this case, the chip selection signal CSX is input to a latch circuit 30 formed by two inverters 34 and 35 connected in a reverse parallel relationship, through two stage inverters 31 and 32 and a transfer gate 33, and is further output as the activation signal CS through two stage inverters 36 and 37. In this construction, when the chip selection signal CSX is "H" level, an "H" level signal is input to the latch circuit 30 and a "L" level signal is output from the latch circuit 30. Therefore, the activation circuit CS becomes "L" level to maintain the address register 7 in an inactive state. Conversely, when the chip selection signal CSX is "L" level, since a "H" level signal is output from the latch circuit 30, the activation signal CS becomes "H" level to activate the address register 7.
On the other hand, for one of the inverter 34 of the latch circuit, a power source voltage Vout is supplied from an initialization setting circuit 20a which will be discussed later (see FIG. 3). For the other inverter 35, power source voltage Vcc is directly supplied from a high potential power source line (not shown) similarly to other circuits. Upon ON set of power (Vcc) supply for such semiconductor memory device, by an operation of the initialization setting circuit 20a, the power source voltage Vout is supplied to the inverter 34 with a delay from the supply of the power source voltage Vcc for the inverter 35. Therefore, upon ON-set of the power supply, because of the operation of the inverter 35 in advance of initiation of the operation of the inverter 34 in the latch circuit 30, the potential at the input terminal A of the latch circuit 30 becomes "H" level, and by this operation of the inverter 35, the output signal of the latch circuit 30 is latched at "H" level after the power supply for the inverter 34.
FIG. 2 shows one example of construction of the above-mentioned initialization setting circuit 20a.
In this figure, for the input terminal of a CMOS inventer 21 (p channel transistor TR3 and n channel transistor TR4), the source of an n channel transistor TR1 is connected. The drain and the gate of the n channel transistor TR1 are connected to a high potential power source line Vcc. On the other hand, to the input terminal of the inverter 21, the drain of a p channel transistor TR2 is connected, which has the source connected to th

REFERENCES:
patent: 4001609 (1977-01-01), Sickert
patent: 5124951 (1992-06-01), Slemmer

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