Initialization of electrically erasable non-volatile semiconduct

Details Initialization of electrically erasable non-volatile semiconduct Initialization of electrically erasable non-volatile semiconduct

1997-05-19

1998-03-24

Nelms, David C.

Static information storage and retrieval

Floating gate

Particular biasing

36518511, 36518529, G11C 2900

Patent

active

057320195

ABSTRACT:
In a method of initializing an electrically erasable non-volatile semiconductor memory device including a memory cell array composed of a plurality of blocks, an erasing operation to each of the memory cell blocks is first executed until a threshold voltage of each memory cell of the each memory block is equal to or lower than a first predetermined value which is lower than a second predetermined value as a final upper limit of a final distribution of threshold voltages of all the memory cells in the each memory block. Next, a programming back operation is executed to the each memory block until each memory cell has the threshold voltage equal to or higher than a third predetermined value as a final lower limit. Finally, a verifying operation is executed to the each memory block to ensure that all the memory cells of the each memory block have the threshold voltages lower than the upper limit.

REFERENCES:
patent: 5297096 (1994-03-01), Terada
S. Yamada et al. "A Self-Convergence Erasing Scheme for a Simple Stacked Gate Flash EEPROM" IEDM Technical Digest, 1991, pp. 307-310.
K. Oyama et al."A Novel Erasing Technoloby for 3.3V Flash Memory With 64Mb Capacity and Beyond" IEDM Technical Digest, 1992, pp. 607-610.

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