Static information storage and retrieval – Radiant energy
Reexamination Certificate
2002-06-07
2003-06-17
Elms, Richard (Department: 2824)
Static information storage and retrieval
Radiant energy
C365S185320
Reexamination Certificate
active
06580630
ABSTRACT:
CROSS-REFERENCE TO RELATED APPLICATION
This application claims the priority benefit of Taiwanese application serial no. 91106568, filed on Apr. 2, 2002.
BACKGROUND OF THE INVENTION
1. Field of the Invention
The invention relates in general to an initialization method of a semiconductor memory, and more particularly, to an initialization method of a P-type silicon nitride read only memory (NROM).
2. Description of the Related Art
The flash memory is a kind of electrically erasable and programmable read only memory (EEPROM) with the capability of saving, reading and erasing data multiple times. Moreover, the data saved in the flash memory does not disappear even when the electricity is interrupted. It thus has become one of the most commonly used memory devices for personal computers and electronic equipment.
The typical flash memory uses a doped polysilicon layer to fabricate the floating gate and the control gate. When a memory is programmed, appropriate programming voltages are applied to the source region, the drain region and the control gate, respectively. The electrons then flow from the source region to the drain region via the channel. In this process, some of the electrons tunnel through the tunneling oxide layer under the floating gate and are evenly distributed in the control gate. The electron tunneling effect through the tunneling oxide to the control gate can be divided into two situations. One is called “channel hot-electron injection”; the other is called “Fowler-Nordheim tunneling”. Normally, channel hot-electron injection is applied to program the flash memory, and Fowler-Nordheim tunneling is applied to the side of the source region and the channel region when erasing. However, if the tunneling oxide layer under the floating gate has weak point, a leakage current of the device is easily caused to affect the reliability of the device.
One conventional method of resolving the problem of device leakageuses a charge trap layer to replace the polysilicon floating gate. The material of the charge trap layer includes silicon nitride. An EEPROM with a stacked gate structure made of a silicon oxide/silicon nitride/silicon oxide (ONO) stacked layer is thus formed. Since the material of the charge trap layer is silicon nitride, this kind of EEPROM is called silicon nitride read only memory (NROM). As the silicon nitride layer has the function of trapping charges, the electrons injected into the silicon nitride floating gate are not uniformly distributed. Instead, the electrons are distributed in a Gaussian distribution in the local area of the silicon nitride floating gate. Since the injected electrons are concentrated in a local area of the silicon nitride floating gate, the sensitivity of the weak points is small, and the device leakage does not easily occur.
Another advantage of using the silicon nitride floating includes that the electrons are locally stored in the channel region close to the upper part of the source or drain region. Therefore, while programming, voltages can be applied to the source/drain region at two sides of the stacked gate and the control gate respectively, so that a Gaussian distribution of electrons is generated in the silicon nitride floating gate near another side of the source/drain region. By changing the voltages applied to the control gate and the source/drain region, two groups of Gaussian distributed of electrons, one group of Gaussian distributed of electrons, or non-existence of electrons can be obtained in the floating gate. Therefore, using silicon nitride as the material for fabricating the floating gate, four statuses can be written into a single memory cell of the flash memory. The flash memory is a kind of a 1 cell 2 bit flash memory.
FIG. 1
shows a structure of conventional silicon nitride read only memory. The silicon nitride read only memory comprises a substrate
100
, a silicon oxide/silicon nitride/silicon oxide (ONO) layer
102
on the substrate
100
, and a gate conductive layer
110
on the ONO layer
102
. The ONO layer
102
further comprises the silicon oxide layer as the tunneling oxide layer
104
, the silicon nitride layer
106
, and the silicon oxide layer
108
as the dielectric layer. The gate conductive layer
110
includes a polysilicon layer. A source region
112
and a drain region
114
are formed in the substrate
100
at two sides of the ONO layer
112
. The silicon nitride read only memory further comprises a channel region
116
under the ONO layer
102
and between the source region
112
and the drain region
114
. In addition, pocket implant regions
118
are formed in the substrate
100
between the ONO layer
102
and the drain region
114
, and between the ONO layer
102
and the source region
112
.
In the conventional silicon nitride read only memory, the source region
112
, the drain region
114
are doped with the same conductive type, for example, P-type or N-type. Thus, a P-type silicon nitride read only memory has P-type source region
112
, drain region
114
. The pocket implant regions
118
are doped with N-type dopants to increase the PN junction concentration so as to increase the electric field.
In the typical process for fabricating the silicon nitride read only memory, due to the influence of the process environment, for example, using plasma to generate electrons from the substrate, some electrons
120
are stored in the silicon nitride layer
106
to cause a non-uniform program of the read only memory. The electrons
120
stored into the silicon nitride layer
106
are non-uniform and cause different initialization statuses for each device. In addition, the electrons stored in the silicon nitride layer
106
are difficult to eliminate and cause the difficulty when used for the first time. To solve the above problem, one can only avoid the injection of electrons into the silicon nitride layer
106
. A good initialization method is still lacking.
SUMMARY OF THE INVENTION
The invention provides an initialization method of a P-type silicon nitride read only memory. After the P-type silicon nitride read only memory is fabricated, an ultra-violet light is uniformly radiated on the P-type silicon nitride read only memory. Consequently, a uniform distribution of electron traps is obtained in the silicon nitride layer of the P-type silicon nitride read only memory. The device is thus maintained at a status with a low threshold voltage (Low|Vt|) to achieve an initialization effect.
In the invention, using the radiation of an ultra-violet light, the device can obtain a unique threshold voltage Vt no matter what the process condition is.
Both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the invention, as claimed.
REFERENCES:
patent: 6437398 (2002-08-01), Widdershoven
“M27C64A: 64 Kbit (8Kb×8) UV EPROM and OTP EPROM”, Sep. 2000, STMicroelectronics.
Huang Shou-Wei
Liu Chien-Hung
Pan Shyi-Shuh
Hur Jung H.
Macronix International Co. Ltd.
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