Initial phase-loading circuit for a fractionally-spaced linear e

Details Initial phase-loading circuit for a fractionally-spaced linear e Initial phase-loading circuit for a fractionally-spaced linear e

1995-04-28

1998-01-20

Chin, Stephen

Pulse or digital communications

Equalizers

Automatic

370537, H04L 2701

Patent

active

057107947

ABSTRACT:
An initial phase-loading circuit (IPLC) for a fractionally-spaced linear equalizer (FSLE) includes a signal coupling component adapted to be coupled to the FSLE in a configuration so as to selectively introduce time-shifted discrete signals. The FSLE includes a set of initial filter tap coefficients that provide a discrete signal to the FSLE, perform discrete signal equalization using the FSLE at least until substantial convergence of the filter tap coefficients, and provide to the FSLE a time-shifted discrete signal to replace the previously provided discrete signal.

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J. D. Wang and J. J. Werner, Twenty-Second Annual Asilomar Conference on Signals, Systems, and Computers, Session MP3: "Communications Applications" in Pacific Grove, California, On The Transfer Function Of Adaptive T/4 Equalizers, Nov. 1, 1988, Maple Press.
W. Y. Chen et al, Technical memorandum to assist Standards Committee Ti-Telecommunications, Standards Project: T1E1.4/92-149, "Design of Digital Carrierless AM/PM Transceivers," Aug. 19, 1992.
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