Inhibit write apparatus and method for preventing bus lockout

Details Inhibit write apparatus and method for preventing bus lockout Inhibit write apparatus and method for preventing bus lockout

1993-01-12

1994-03-08

Heckler, Thomas M.

Boots, shoes, and leggings

364DIG1, 36424292, 3642281, 3642317, 36424341, G06F 1336

Patent

active

052934969

ABSTRACT:
A User bus lockout prevention mechanism for use in a time-shared busy multiple bus User, computer architecture where bus Users include private cache systems which perform a cache cycle when a WRITE TO MEMORY instruction occurs on the bus to determine if data cached from main memory has been overwritten in main memory. A User can be locked out from use of the bus if a synchronism occurs between repetative cache cycles and periodicity of the Retry mechanism of the User. Bus lockout is prevented by the User with the cache issuing an INHIBIT WRITE to the bus when a cache cycle is being performed. Other Users inhibit issuing WRITE TO MEMORY requests to the bus until the INHIBIT WRITE signal terminates. Bus requests other than a write request may be issued to the bus during INHIBIT WRITE.

REFERENCES:
patent: 4831581 (1989-05-01), Rubinfeld
patent: 5072369 (1991-12-01), Theus et al.
patent: 5091845 (1992-02-01), Rubinfeld

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