Inherently compensated clocking circuit for dynamic random acces

Details Inherently compensated clocking circuit for dynamic random acces Inherently compensated clocking circuit for dynamic random acces

1998-06-30

1999-12-21

Nguyen, Tan T.

Static information storage and retrieval

Addressing

Sync/clocking

365194, 365211, G11C 800

Patent

active

060058242

ABSTRACT:
A clock delay circuit which creates control signals relative to a clock signal which vary in relation to inherent variables arising from manufacturing process, temperature and voltage influences on a memory array. The clock delay circuit preferably comprises a pair of spare word lines and a pair of spare bit lines of the memory, each of which extends across the memory array. Signals conducted along the spare word and bit line create a signal which is supplied to a counter and decoder to supply a plurality of control signals having a timing relationship established relative to the clock. The spare word line and spare bit line comprise electrical characteristics affecting signal propagation time similar to a signal propagation time along one of an actual word line or actual bit line, respectively.

REFERENCES:
patent: 4866676 (1989-09-01), Crisp et al.
patent: 5208778 (1993-05-01), Kumanoya et al.
patent: 5231319 (1993-07-01), Crafts et al.
patent: 5270977 (1993-12-01), Iwamoto et al.
patent: 5323348 (1994-06-01), Mori et al.
patent: 5325334 (1994-06-01), Roh et al.
patent: 5373472 (1994-12-01), Ohsawa
patent: 5375095 (1994-12-01), Yamada et al.
patent: 5386386 (1995-01-01), Ogihara
patent: 5388104 (1995-02-01), Shirotori
patent: 5440517 (1995-08-01), Morgan et al.
patent: 5471482 (1995-11-01), Byers et al.
patent: 5499214 (1996-03-01), Mori et al.
patent: 5502675 (1996-03-01), Kohno et al.
patent: 5517450 (1996-05-01), Ohsawa et al.
patent: 5577004 (1996-11-01), Lesham
patent: 5619463 (1997-04-01), Malhi
patent: 5623640 (1997-04-01), Nakabo
patent: 5650975 (1997-07-01), Hamade et al.
patent: 5668755 (1997-09-01), Hidaka
patent: 5684751 (1997-11-01), Manning
patent: 5689466 (1997-11-01), Quereshi
patent: 5694355 (1997-12-01), Skjaveland et al.
patent: 5825682 (1998-10-01), Fukui
"Automatic Small Computer System Interface Termination Circuit for Narrow/Wide Devices on Wide Bus", IBM Technical Disclosure Bulletin, vol. 40, No. 4, Apr. 1997, New York, US, pp. 79-82.
"BI-0316 Mass Storage Module", Dec. 6, 1996, Brand Innovators B.V. XP002071927. Available from Internet<URL:http/www.brandinnovators.com/manual/bi0316/book.sub.- 33.htm> .

Affiliated with

Also associated with

Rating

Inherently compensated clocking circuit for dynamic random acces does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Inherently compensated clocking circuit for dynamic random acces, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Inherently compensated clocking circuit for dynamic random acces will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-511887