Radiant energy – Invisible radiant energy responsive electric signalling – Infrared responsive
Reexamination Certificate
2002-09-23
2004-01-06
Hannaher, Constantine (Department: 2878)
Radiant energy
Invisible radiant energy responsive electric signalling
Infrared responsive
Reexamination Certificate
active
06674081
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a structure and a manufacturing method of an infrared detecting element using ferroelectric thin film material to detect the intensity of infrared radiation from an object.
2. Description of the Background Art
[Background Art of Infrared Detecting Element]
Objects and human bodies at room temperature radiate infrared rays (heat rays) of approximately 10 &mgr;m in wavelength which can be measured to detect the presence of them and obtain temperature information without contact. This infrared detection is applied to various uses like automatic door, intruder alarm, cooking monitor of microwave oven, chemical measurement, and the like.
The key device of prime importance for such measurement is an infrared sensor. There are generally two types of infrared sensors, i.e., quantum infrared sensor and thermal infrared sensor.
The quantum infrared sensor is highly sensitive and excellent in sensing ability while it requires cooling resulting in increase in size of the entire device and thus has a problem in practical use. On the other hand, the thermal infrared sensor is somewhat inferior to the quantum infrared sensor in terms of sensitivity while it is appropriate for practical use because of its advantage that operation at room temperature is possible.
Ferroelectric materials have temperature dependencies of both of polarization and dielectric constant as shown in
FIG. 26
, and these characteristics are applicable to thermal infrared sensors. The former effect is related to conventional pyroelectric (PE) bolometers and the latter effect is related to dielectric bolometers (DB).
Accordingly, various thermal infrared sensors have been proposed including those utilizing pyroelectric effect, resistance bolometer, dielectric bolometer, thermopile, Golay cell, and the like. For example, an infrared image sensor using the pyroelectric effect is disclosed in Proc. 8th IEEE Int. Symp. Appl. Ferroelectronics (1992), pp. 1-10 (“PYROELECTRIC IMAGING” by Bernard M. Kulwicki et al.).
In particular, the dielectric bolometer which applies electric field to detect the change of dielectric constant with respect to temperature has a higher sensitivity than those of other sensors and it requires no chopper. Because of these excellent features, the dielectric bolometers are considered prospective in terms of practical use.
Further, an advanced infrared sensing is expected that is applied to infrared image sensors (thermography) capable of providing temperature distribution of objects and scenery without contact.
In order to accomplish infrared imaging, infrared image pickup devices operating at room temperature have been produced as prototypes by bump-coupling an array of pyroelectric ceramic and a silicon FET (field effect transistor) or forming a thin-film and low-resistive bolometer on a microbridge structure which is coupled with a silicon FET array.
Regarding these devices, a higher performance is expected such as an enhanced resolution by increase in sensitivity and number of pixels and the like. However, conventional pyroelectric infrared sensors and infrared sensors in the form of resistance bolometers are limited in sensitivity or have an insufficient number of pixels.
FIG. 27
shows a cross sectional structure of a conventional pixel cell
20
in such an infrared detecting element coupled with a silicon FET array.
Referring to
FIG. 27
, pixel cell
20
includes a silicon oxide film
304
deposited on an Si substrate
300
, a MOS transistor Tr
1
formed in an opening of silicon oxide film
304
, an infrared detecting capacitor CF formed being adjacent to MOS transistor Tr
1
and constituted of a lower electrode
308
(stacked Pt/Ti films), a ferroelectric film
310
(BST film) and an upper electrode
312
(Al film), and a trench
330
opened to extend from the rear side of Si substrate
300
to a predetermined depth directly below infrared detecting capacitor CF.
MOS transistor Tr
1
includes source/drain regions
320
and
324
formed in a main surface of the Si substrate in the opening of silicon oxide film
304
that are impurity regions of opposite polarity to that of the substrate, a channel layer
322
formed in the main surface of the Si substrate between source/drain regions
320
and
324
, a gate oxide film
302
deposited on the main surface of the Si substrate directly above the channel layer, and a polysilicon gate electrode
314
formed on gate oxide film
302
.
Lower electrode
308
is deposited on a silicon nitride film
306
which is deposited on silicon oxide film
304
to serve as an interlayer insulating film. Lower electrode
308
contacts source/drain region
320
.
On gate electrode
314
, an interconnecting line
316
is provided that is formed of the same interconnection layer as lower electrode
308
, an interconnecting line
318
formed of the same interconnection layer as lower electrode
308
contacts source/drain region
324
.
Trench
330
is provided in order to reduce thermal loss as much as possible to Si substrate
300
having a high thermal conductivity since pixel cell
20
is a thermal infrared sensor and a rise in temperature of the cell directly affects the intensity of an output signal.
Accordingly, it is desirable in terms of process to make the thickness of Si substrate as thin as possible that remains between trench
330
and silicon oxide film
304
. On the other hand, since it is not preferable that the thickness of remaining Si substrate differs between pixel cells
20
, an etching stopper layer is formed on the front side of the Si substrate when trench
330
is formed by etching from the rear side. For example, the etching stopper layer can be generated by implanting ions (e.g. at least 3×10
16
cm
−3
in concentration) like boron (B) from the front side of the substrate to reduce the etching rate of Si.
A method of manufacturing pixel cell
20
shown in
FIG. 27
is explained below in conjunction with respective cross sections showing the first to twelfth steps of the method.
FIGS. 28
to
39
are cross sectional views respectively illustrating the first to twelfth steps.
Referring to
FIG. 28
, on the surface of Si substrate
300
which has been RCA-cleaned, silicon oxide film
304
is formed through thermal oxidation in the first step.
The thermal oxidation is performed under the conditions, for example, that oxidation at 1000° C. and 51 l/min of oxygen flow rate for 5 minutes is performed and thereafter oxidation at 1000° C., 5 l/min of oxygen flow rate and 4.5 l/min of hydrogen flow rate for 180 minutes is performed. The thermal oxidation under these conditions forms an about 650-nm-thick oxide film for example.
Further, an alignment mark
301
is formed on the rear side of the substrate by anisotropic dry etching or the like.
Referring to
FIG. 29
, in the second step, an opening is formed in a predetermined region
303
of silicon oxide film
304
by etching. MOS transistor Tr
1
is formed in this region
303
as described later.
Referring to
FIG. 30
, a resist pattern
305
is used as a mask for ion implantation of ion species into channel portion
322
of MOS transistor Tr
1
, the ion species corresponding to the conductivity type of the channel portion
322
. Then, annealing is performed for activation.
Referring to
FIG. 31
, gate oxide film
302
is deposited on the Si substrate through thermal oxidation and thereafter a polysilicon
307
is deposited by CVD (Chemical Vapor Deposition) or the like that forms the gate electrode.
Referring to
FIG. 32
, polysilicon
307
is patterned and etched by anisotropic etching like RIE (Reactive Ion etching) to form gate electrode
314
.
Referring to
FIG. 33
, the gate pattern is used as a mask to etch away gate oxide film
302
on opening
303
and silicon oxide film
304
, and then gate electrode
314
and silicon oxide film
304
are used as a mask to diffuse impurities to generate source/drain regions
320
and
324
.
Referring to
FIG. 34
, silicon nitride film
306
is deposited b
Hashimoto Kazuhiko
Kishihara Hiroyuki
Kubo Ryuichi
Mukaigawa Tomonori
Noda Minoru
Armstrong, Kratz, Quintos, Hanson&Brooks, LLP
Hannaher Constantine
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