Dynamic information storage or retrieval – Binary pulse train information signal – Including sampling or a/d converting
Reexamination Certificate
2007-12-11
2011-12-27
Haley, Joseph (Department: 2627)
Dynamic information storage or retrieval
Binary pulse train information signal
Including sampling or a/d converting
C369S047280, C369S053350, C369S059220
Reexamination Certificate
active
08085639
ABSTRACT:
An A/D converter samples a read signal in synchrony with a system clock sclk having a fixed frequency, to perform an A/D conversion. A fluctuation compensator is configured as an internal-feedback-type compensation filter, and suppresses fluctuation of a digital signal output from the A/D converter. A digital PLL uses an interpolator to generate, by interpolation, a sampled value of the read signal at a timing in synchrony with a channel frequency, and uses NCO to generate a synchronizing clock and an interpolated-phase signal that is fed back to the interpolator. A binarization circuit binarizes the read signal based on the interpolated value output from the interpolator. The frequency characteristic of the fluctuation compensator is controlled based on the frequency value output from the loop filter.
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IB of WIPO, International Preliminary Report on Patentability, PCT/JP2007/073827,Sep. 17, 2009, 4 pages.
Foley & Lardner LLP
Haley Joseph
NEC Corporation
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