Dynamic information storage or retrieval – Binary pulse train information signal – Binary signal gain processing
Patent
1998-04-24
2000-08-01
Hindi, Nabil
Dynamic information storage or retrieval
Binary pulse train information signal
Binary signal gain processing
G11B 700
Patent
active
060976853
ABSTRACT:
A structure for detecting a phase error for causing a PLL of an information reproducing apparatus to be locked and for selecting Viterbi determination mode, MSB determination mode (for obtaining a phase error detection timing corresponding to MSB of output data of an A/D converter disposed on the preceding stage of a Viterbi decoder) is disclosed. One of the three modes is selected corresponding to the state of the PLL. A Viterbi timing generating circuit, an MSB timing generating circuit, and a frequency lock mode timing generating circuit are provided. Phase error detection timings generated by the three circuits are selectively supplied to a phase error detecting circuit by a sampling pulse selecting switch. The selected phase error detection timing is switched between the acquisition mode and the tracking mode.
REFERENCES:
patent: 5901128 (1999-05-01), Hayashi et al.
Chiba Takayoshi
Horigome Junichi
Yamaguchi Shigeo
Hindi Nabil
Oh Seong-Kun
Sony Corporation
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