Excavating
Patent
1994-11-01
1997-02-04
Envall, Jr., Roy N.
Excavating
369 60, G06F 1110, H03M 1312, G11B 2736, H04N 576
Patent
active
056006640
DESCRIPTION:
BRIEF SUMMARY
TECHNICAL FIELD
The present invention relates to an information reproducing apparatus suitable for use in a case where information recorded on, for example, a magnetic disc, a magnetic tape, an optical disc, a magneto-optical disc and so on is decoded with a maximum likelihood decoding method such as a Viterbi decoding method or the like.
BACKGROUND ART
A partial response is used as a modulation code used in a magnetic recording and reproducing apparatus or an optical recording and reproducing apparatus. Of kinds of the partial response, PRS (1,1) (class I), PRS (1,-1), PRS (1,0 -1) (class IV) and so on are used frequently. An arithmetic circuit 101 shown in FIG. 6(a) uses the PRS (1,0,-1). Arithmetic circuits 102, 103 shown in FIG. 6(b) use the PRS (1,-1). A system polynomial G(D) of the PRS (1,0,-1) is G(D)=1-D.sup.2 and a system polynomial G(D) of the PRS (1,-1) is G(D)=1+D, where reference letter D represents a delay operator.
The arithmetic circuit 101 is a circuit which successively outputs data of 1, 0 and -1 when an independent logic 1 is input. The arithmetic circuits 102, 103 are circuits which successively output data of 1 and -1 when an independent logic 1 is input.
The arithmetic circuit 101 (PRS(1,0,-1)) shown in FIG. 6(a) has the system polynomial of G(D)=1-D.sup.2 and hence always calculates input data y.sub.k inputted at a certain sampling time k as a two previous sample y.sub.k-2. Accordingly, an odd number sample and an even number sample are substantially independent of each other and can be regarded as independent series of the partial response PRS (1,-1). The circuit shown in FIG. 6(a) is equivalent to a circuit shown in FIG. 6(b) in which the odd and even number samples of input data are respectively supplied to and processed by the arithmetic circuits 102, 103 for calculating the partial response PRS (1,-1) by switching a switch 104 and outputs of the arithmetic circuits are synthesized by a switch 105 to be output.
Decoding in which the arithmetic circuits 102, 103 (PRS (1,-1)) are used with being interleaved is substantially the same as decoding carried out by the arithmetic circuit 101 (PRS(1,0,-1)). Here, the partial response PRS (1,0,-1) will be explained by way of example.
The partial response PRS (1,0,-1) itself has the property of permitting an error to be propagated and, hence, one bit error caused under a certain condition, may cause a fatal error. Therefore, in order to prevent such an error from being caused, it is necessary to pre-code data before recording them. This pre-coding can be carried out by effecting a reverse conversion of the partial response.
FIG. 7 shows a total arrangement of a conventional for modulating and demodulating the partial response through such precoding. In FIG. 7, a pre-coder 111 carries out a process of 1/(1-D.sup.2).
Recorded data are converted by the pre-coder 111 into pre-coded data varying between a value 1 of the recorded data and a value -1 thereof by utilizing a correlation between data of the recorded data. The thus converted data are output to a recording channel circuit 112.
The recording channel circuit 112 is not an explicitly provided circuit rather a function which is inherently possessed by a magnetic recording and reproducing system and is represented in FIG. 7 as an equivalent circuit. In this circuit (that is, when the data are magnetically recorded and then reproduced), an arithmetic processing circuit 113 subject the output from the pre-coder 111 to an arithmetic processing of (1-D).
At this time, a noise generated in a practical magnetic recording channel is treated as one to be added to a result of the calculation by an adder 114. Data to which the noise is added (data reproduced after magnetically recorded) are from the recording channel circuit 12 an arithmetic processing circuit 115. The arithmetic processing circuit 115 subjects the output from the recording channel circuit 112 to an arithmetic processing of (1+D).
As shown in FIG. 8, a signal output from the recording channel circuit 112 is set at any one of th
REFERENCES:
patent: 3851306 (1974-11-01), Patel
patent: 5220568 (1993-06-01), Howe et al.
patent: 5329535 (1994-07-01), Coker
Envall Jr. Roy N.
Moise Emmanuel L.
Sony Corporation
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