Electrical computers and digital processing systems: processing – Processing architecture – Microprocessor or multichip or multimodule processor having...
Reexamination Certificate
1998-08-31
2001-08-28
Donaghue, Larry D. (Department: 2154)
Electrical computers and digital processing systems: processing
Processing architecture
Microprocessor or multichip or multimodule processor having...
C712S234000
Reexamination Certificate
active
06282632
ABSTRACT:
BACKGROUND OF THE INVENTION
(1) Field of the Invention
The present invention relates to an information processor that has an operation flag register reflects the result of an operation in an instruction by updating operation flags.
(2) Description of the Related Art
Recently, information processors, for instance, microcomputers, have been drastically developed and used in a variety of fields.
Generally speaking, an information processor increases the throughput by executing a plurality of instructions in such as the VLIW (Very Long Instruction Word) and the superscalar method in parallel.
A conventional information processor includes a flag register for storing operation flags, for instance, a carry flag or an overflow flag. When executing an arithmetical instruction, the conventional information processor creates operation flags and updates the flag register. The conventional information processor refers to an operation flag that is the condition in a conditional branch instruction. As a result, the compiler or the assembler for the information processor has to schedule the instructions in a program so that an arithmetical instruction that changes the operation flags is not executed between an arithmetical instruction and a conditional branch instruction.
It is pretty much difficult for the compiler or the assembler to schedule such instructions for a processor that executes instructions in parallel in order to increase the throughput (for instance, a VLIW processor).
An information processor for which a compiler may schedule instructions easily without changing operation flags has developed. Such an information processor includes a plurality of operation flag registers, and each of the instructions designates a flag register that is to be updated (refer to, for instance, “PowerPC601 User's Manual, IBM Microelectronics”).
FIGS. 1A and 1B
show the specification of arithmetical instructions of the conventional information processor and the construction of the operation flag registers.
The information processor includes two flag registers, that is, flag register CR (Condition Register) and flag register XER (Integer Exception Register) shown in FIG.
1
B. The flags are set in these registers as shown in FIG.
1
B.
For the information processor, four different arithmetical instructions that perform the same arithmetical operation are prepared (
FIG. 1A
shows only add instructions).
FIG. 1A
shows when a period “.” is added to the mnemonic (“add”), the operation flag in flag register CR is updated, and when the alphabet “o” is added to the mnemonic, the operation flag in flag register XER is updated.
For one add instruction, four kinds of instruction are prepared. The instruction to update no flag register, the instruction to update flag register CR, the instruction to update flag register XER, and the instruction to update flag register CR and flag register XER are prepared.
It is easy for the compiler or the assembler to schedule instructions using such instructions. For instance, it is easy to arrange an arithmetical instruction to update no flag register between an arithmetical instruction to update flag register CR and a conditional branch instruction.
According to the conventional art, however, the length of an instruction code and the code size are increased since one of four instruction codes (op (operation) codes) has to be assigned to an instruction depending on which flag register should be updated.
For instance, an instruction code for a “PowerPC601” processor is lengthy. This is because one bit of field showing whether a period “.” is included and another one bit of field showing whether the alphabet “o” is included are set in almost all such instruction codes.
A plurality of methods for updating operation flags are prepared for each instruction. As a result, a relatively large-scale hardware is necessary for the instruction decoder.
In addition, the operation flag register that is to be updated has to be designated for each instruction according to the conventional art. As a result, when instruction codes are assigned to instructions, the length of the field for designating the operation is increased, and consequently the code size is increased.
SUMMARY OF THE INVENTION
It is accordingly an object of the present invention to provide an information processor that does not increase the code sizes of instruction codes and a program, prevents the hardware size of an instruction decoder from increasing, and enables a compiler or an assembler to schedule instructions easily.
The above-mentioned object is achieved by a processor may include: a flag register for storing a first flag group and a second flag group that includes same kinds of operation flags as the first flag group; an instruction decoding unit for decoding at least two types of instructions, a first-type instruction and a second-type instruction, wherein operations in the first-type and the second-type instructions are different; an execution unit for executing an instruction according to a decoding result and for creating flag data based on an execution result of the instruction; a first update unit for updating, when the first-type instruction has been decoded, the first flag group using the created flag data; and a second update unit for updating, when the second-type instruction has been decoded, the second flag group using the created flag data.
The object may also be achieved by the processor, wherein first-type instructions include compare instructions that compare register data, and second-type instructions include arithmetic logic operation instructions and no compare instruction.
The object may also be achieved by the processor, wherein the second flag group includes a carry flag and an overflow flag as the operation flags of the same kinds as the operation flags in the first flag group.
The object may also be achieved by the processor, wherein the instruction decoding unit activates a flag update signal when decoding an instruction that updates an operation flag, and when decoding the first-type instruction, activates a first-type signal that indicates that a decoded instruction is the first-type instruction, the first update unit updates the first flag group when the flag update signal and the first-type signal are activated, and the second update unit updates the second flag group when the flag update signal is activated and the first-type signal is not activated.
In this construction, whether the first flag group or the second flag group stores the flag data that is created in an operation depends on whether a first-type instruction or a second-type instruction is decoded. In other words, whether the first flag group or the second flag group that include the same kinds of operation flags is updated depends on the instruction type. As a result, it is possible for the processor to use flag groups properly that have the same kinds of flags without increasing the length of instruction codes and the code size of a program.
When decoding an instruction, the instruction decoder judges whether a first-type instruction or a second-type instruction is decoded. As a result, it is possible to realize the processor with low cost without increasing the hardware size of the decoder.
In addition, it is possible for the processor to use the flag groups properly, so that the processor may enable the compiler or the assembler to schedule instructions easily.
The object may be achieved by the processor may further include a branch judgement unit for judging, when the first-type conditional branch instruction has been decoded, a condition using the first flag group, and for judging, when the second-type conditional branch instruction has been decoded, a condition using the second flag group.
In this construction, when executing an operation in which flags are referred to, the processor may use flag groups properly according to the type of the instruction. In other words, the flag group that is referred to depends on whether a first-type conditional branch instruction or a second-type conditional branch instru
Higaki Nobuo
Takayama Shuichi
Tanaka Tetsuya
Donaghue Larry D.
Matsushita Electric - Industrial Co., Ltd.
Price and Gess
LandOfFree
Information processor having duplicate operation flags does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Information processor having duplicate operation flags, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Information processor having duplicate operation flags will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2543891