Electrical computers and digital processing systems: processing – Processing architecture – Array processor
Reexamination Certificate
1998-10-16
2002-09-10
Pan, Daniel H. (Department: 2183)
Electrical computers and digital processing systems: processing
Processing architecture
Array processor
C712S013000, C712S011000, C710S065000, C710S073000, C710S074000, C710S120000, C710S052000, C711S108000, C711S143000
Reexamination Certificate
active
06449707
ABSTRACT:
TECHNICAL FIELD
The present invention relates to the basic structure and the entire structure of a data processing apparatus including a semiconductor memory device, and specifically, to a data processing structure which internally operates and stores data in itself, a data processing structure unit consisting of a plurality of data processing units which transfer data to make interaction with each other, and a data processing structure represented by a semiconductor memory device consisting of the data processing unit or data processing structure unit.
BACKGROUND ART
Recently, data processing apparatuses represented by image data processing, data memory or the like have been developed and available as products. For example, semiconductor memory devices such as a dynamic random access memory (DRAM), a static random access memory (SDRAM), and the like have already been subjected to mass-production and used so as to comply with various specifications. In these data processing apparatuses, it is a basic principle that data to be read out ,is perfectly the same as data to be written, and there originally is a lack of an idea of making any operation processing on data to be written.
In this respect, a proposal has been made as to a concept for modifying a kind of dispersed data processing system into a device, i.e., cells utilizing a quantum phenomenon are realized and disposed as operation factors in a matrix-like array and the cells are caused to make close interactions between each other in accordance with rules set in compliance with purposes (Amamiya Yoshihito and Akazawa Masamichi, “How a quantum phenomenon should be combined with data processing to prepare a LSI with a quantum effect device”, Applied Physics, Vol. 64, No. 8, pages 765 to 768). In a device realized by the concept, for example, when four adjacent cells are “1” where a center cell surrounded by eight cells is “1”, the center cell is next changed to “0” in a step. When two adjacent cells are “1”, the state of “1” is maintained. Where the center cell is “0”, the center cell is not changed to “1” even when two adjacent cells are “2”. Thus, it is said that a change of the state of the center cell and further a change of data in a device can be realized.
However, in the prior art example described above, only an extremely conceptual instruction can be found with respect to realization of a device of a dispersed data processing system. Therefore, in consideration of a specific device, there is a problem as to what will be the form at the level of a device.
The present invention has been made to a situation as described above and has an object of providing a technique of realizing a kind of dispersed data processing system at the level of device, e.g., a special data processing unit or memory structure unit which realizes the technique, a data processing structure unit constructed by providing a plurality of said data processing units, the data processing unit, or a data processing structure comprising the data processing structure unit and a semiconductor memory device comprising the memory structure unit.
DISCLOSURE OF INVENTION
A data processing unit according to the present invention basically comprises: input for inputting first data from outside; an operation circuit for operating the first data to generate second data; memory for storing the second data; output for outputting the second data stored in the memory to the outside; and a controller for controlling the memory to enable storing and outputting of the second data.
The data processing unit may comprise a data reproduction circuit for reproducing the second data outputted. Further, the data processing unit may comprise a write circuit which is for inputting third data from the outside and writes the third data as the second data into the memory, and a read circuit for reading data stored in the memory. The operation circuit of the data processing unit may be a logic circuit among a group of logic circuits consisting of an identity logic circuit, an inversion logic circuit, an exclusive OR circuit, an exclusive AND circuit, an OR circuit, and an AND circuit, and may comprise at least two logic circuits among a group of logic circuits consisting of an identity logic circuit, an inversion logic circuit, an exclusive OR circuit, an exclusive AND circuit, an OR circuit, and an AND circuit, and a selector for selecting one output from outputs of the at least two logic circuits.
A first data processing structure unit according to the present invention is a dimer-like structure unit consisting of two data processing units each described above, in which the output of one data processing unit is electrically connected with the input of the other data processing unit. Further it is preferred that the two data processing units are arranged adjacent to each other.
A second data processing structure unit according to the present invention is a dimer-like structure unit consisting of first, second, and third data processing units as described above, in which the output of the first data processing unit is electrically connected with the input of the second data processing unit, and the output of the second data processing unit is electrically connected with the input of the third data processing unit. In this trimer-like data processing structure unit, it is preferred that the first and second data processing units, as well as the second and third data processing units, are arranged adjacent to each other.
A first data processing structure according to the present invention is a structure comprising a plurality of data processing units as described above, in which the first data of each data processing unit is one or two or more data items, and all or a part thereof is the second data outputted from the output of other one or two or more data processing units. The first data processing structure preferably comprises connection circuits for electrically connecting the input of each of the data processing units with the output of a data processing unit other than the data processing units itself.
A second data processing structure according to the present invention comprises two dimer-like data processing structure units each described above, and connection circuits for electrically connecting a first or second data processing unit of one of the data processing structure units with a first or second data processing unit in the other data processing structure unit.
A third data processing structure according to the present invention comprises two trimer-like data processing structure units each described above, and connection circuits for electrically connecting a first, second, or third data processing unit of one of the data processing structure units with a first, second, or third data processing unit in the other data processing structure unit.
In the second and third data processing structures constructed by a polymer-like data processing structure unit including the dimer-like and trimer-like units, it is preferred that two data processing structure units are arranged adjacent to each other, like an array. Where these data processing structures comprise a plurality of bit lines and a plurality of word lines crossing the bit lines, it is preferred that the data processing units in the data processing structure unit are provided at a cross-position between the bit lines and the word lines.
A fourth data processing structure according to the present invention comprises a plurality of data processing units, and each of the data processing units comprises: an operation circuit for operating on first data inputted from other one or two or more data processing units, by one of a group of logic operations consisting of identity, inversion, exclusive OR, OR, and AND, to generate second data; memory for storing the second data; output for outputting the second data stored in the memory to one or two or more other data processing units than each of the data processing units itself; and a controller for controlling the memory to enable storing and outputting of the second data
Fujitsu Limited
Haynes Mark A.
Haynes Beffel & Wolfeld LLP
Pan Daniel H.
LandOfFree
Information processing unit, information processing... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Information processing unit, information processing..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Information processing unit, information processing... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2901710