Information processing unit having a multiplexed bus and a bus c

Details Information processing unit having a multiplexed bus and a bus c Information processing unit having a multiplexed bus and a bus c

1992-03-10

1996-09-17

Sheikh, Ayaz R.

Boots, shoes, and leggings

395181, 395299, 364DIG1, 364230, 3642301, 364240, 3642426, 3642427, G06F 1314

Patent

active

055577539

ABSTRACT:
A high-speed information processing in the information processing unit having a multiplexed bus is provided. A unit having a bus grant is stored in the next lowest priority unit memory circuits, and in the next bus arbitration cycle, bus arbitration is carried out by setting the lowest priority to the unit stored in the next lowest priority unit memory circuits. When a fault occurs in one of a plurality of buses and then the faulty bus recovered a normal operation status, the bus status supervising circuits output has fault recovery detecting signals and match the memory contents of the next lowest priority unit memory circuits together. With the above arrangement, an average bus waiting time can be minimized and the bus waiting time can be limited.

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