Patent
1996-02-22
1997-07-22
Beausoliel, Jr., Robert W.
39518322, G06F 1100
Patent
active
056511124
ABSTRACT:
An information processing system capable of performance measurement by the use of a small amount of mounted hardware. The information processing system having central processors installed therein comprises a control circuit, and a performance measurement validation register for specifying whether a performance measurement function is valid or invalid. In a case where the validity of the measurement function has been specified by the register, the control circuit operates one loop in a duplex configuration as a performance measurement facility. At this time, counter #1-counter #3 are used as counters for totalizing performance information. On the other hand, in a case where the invalidity of the measurement function has been specified, both loops in the duplex configuration are operated as the central processors. At this time, the counter #1-the counter #3 are used as timer counters for controlling buses.
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Horie Masanori
Kobayashi Hiroshi
Matsuno Atsushi
Naito Masanori
Saika Toshimasa
Beausoliel, Jr. Robert W.
Hitachi , Ltd.
Hitachi Process Computer Engineering Inc.
Palys Joseph E.
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