Information processing system architecture including two buses

Details Information processing system architecture including two buses Information processing system architecture including two buses

1992-01-29

1993-07-06

Picard, Leo P.

Electricity: electrical systems and devices

Miscellaneous

361415, H01R 900

Patent

active

052259676

ABSTRACT:
An information processing system architecture (ORDI), in which the various constituent elements (B.sub.1 -B.sub.6, A.sub.1 -A.sub.6, C.sub.1 -C.sub.4) comprise a plurality of boards (CDI.sub.i and CGI.sub.j), each embodied by printed circuits carrying a plurality of integrated circuits, and including at least two sets of elements (ENSI.sub.1, ENSI.sub.2), all or some of the elements of one set being identical to all or some of the elements of the other. The sets are associated with two system buses of the parallel type (PSBA, PSBBI) that assure both communications and the transfer of data and electrical energy among the boards. The two buses have a total or partial overlap zone (ZC) between them, on which either one or more elements (C.sub.1 -C.sub.2, C.sub.3 -C.sub.4) common to the two sets exclusively, and elements belonging to the first set (ENSI.sub.1, A.sub.5 and A.sub.6) and/or to the second set (ENSI.sub.2, B.sub.5 and B.sub.6), are connected.

REFERENCES:
patent: 3681665 (1972-08-01), Olds et al.
patent: 3710197 (1973-01-01), Olds et al.
patent: 4470100 (1984-09-01), Rebaudo et al.
"Microprocessing & Microprogramming", vol. 21, Nos. 1-5, Aug. 1987, pp. 333-338, Section 6, Tolerating Bus Failures, p. 337.
"Computer Technology Review", vol. 4, No. 3, 1984, 35-36, 38, Shared Memory Devices Can Link PDP-11s into Load-Balanced Clusters, p. 35, col. 1; p. 36, col. 3, FIG. 1.
"Databus", Jul./Aug. 1987, pp. 14-19, Deventer, N.L., Achtergronden van de VME-Bus; FIG. 1.

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