Information processing apparatus with parallel instruction decod

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395375, 364DIG1, G06F 934, G06F 922, G06F 1200

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active

052747921

ABSTRACT:
An information processing apparatus includes a decoder for decoding an instruction, a general purpose register part including a stack pointer and a plurality of general purpose registers, a special purpose register part including a plurality of special purpose registers, and a processing part coupled to the decoder, the general purpose register part and the special purpose register part for carrying out a predetermined process based on a decoded result from the decoder by selectively using a read out result of one of the general purpose register part and the special purpose register part. A decoding operation of the decoder, a read out operation of the general purpose register part and a read out operation of the special purpose register part are carried out in parallel.

REFERENCES:
patent: 5136696 (1992-08-01), Beckwith et al.
patent: 5148528 (1992-09-01), Fite et al.
patent: 5179530 (1993-01-01), Genusov et al.

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