Information processing apparatus with cache memory and a process

Details Information processing apparatus with cache memory and a process Information processing apparatus with cache memory and a process

1992-10-29

1994-01-04

Dixon, Joseph L.

Boots, shoes, and leggings

364DIG1, 3642434, 3642543, 3642448, G06F 1202

Patent

active

052768503

ABSTRACT:
An information processing apparatus which includes a main memory for storing a plurality of data blocks each having a predetermined size stores a plurality of data blocks. Each data block includes a plurality of words, and each word includes a plurality of byte data. A data memory section in a cache memory for storing a small amount of data as compared with that of the main memory to achieve high-speed processing transfers data from/to the main memory in units of data blocks. A microprocessor generates a request address including desired data block and word addresses in order to access a plurality of desired words in a desired data block in the data memory section. A comparator determines whether a data block corresponding to the data block address is present in the data memory section. The microprocessor reads a plurality of words corresponding to the word address in the plurality of words in the corresponding data block from the data memory section in response to an output from the comparator.

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IBM Technical Disclosure Bulletin, vol. 23, No. 7B, Dec. 1980, pp. 3461-3463; J. Yamour.

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