Information processing apparatus with adjustable system clock

Miscellaneous active electrical nonlinear devices – circuits – and – Signal converting – shaping – or generating – Clock or pulse waveform generating

Reexamination Certificate

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Details

C327S144000

Reexamination Certificate

active

07102408

ABSTRACT:
An information processing apparatus is constructed by a system PLL, a first unit, a second unit, and a system board on which they are mounted. A delay setting circuit in which a variation and delay elements (a gate delay and a line delay) which are equivalent to those of a clock tree circuit for a gate have been set at the designing stage is provided on a signal line of a system clock in the first unit to the second unit. A delay setting circuit in which a variation and delay elements which are equivalent to those of the clock tree circuit for the gate have been set at the designing stage is provided on a signal line of a clock gate signal to the second unit.

REFERENCES:
patent: 5768213 (1998-06-01), Jung et al.
patent: 6003118 (1999-12-01), Chen
patent: 6028816 (2000-02-01), Takemae et al.
patent: 2004/0049708 (2004-03-01), Thomas et al.
patent: 2004/0232959 (2004-11-01), Hohnel
patent: 3209511 (1991-09-01), None
patent: 2000-29561 (2000-01-01), None
patent: 2000-347764 (2000-12-01), None

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