Electrical computers and digital processing systems: processing – Architecture based instruction processing
Reexamination Certificate
2008-03-04
2008-03-04
Coleman, Eric (Department: 2183)
Electrical computers and digital processing systems: processing
Architecture based instruction processing
C712S205000
Reexamination Certificate
active
07340587
ABSTRACT:
An information processing apparatus performing pipeline control includes a first fetch cue fetching a non-branch location instruction, a second fetch cue fetching a branch location instruction, a fetch circuit which carries out arithmetic of a fetch address, fetch it to the first fetch cue or the second fetch cue, and outputs a first fetch cue or a second fetch cue instruction to a decode circuit, a decode circuit which receives and decode an instruction code fetched to the first fetch cue or the second fetch cue, and an execution circuit performing execution of an instruction based on a decoding result, wherein the above-mentioned fetch circuit includes a selective circuit which selects which instruction of the first fetch cue or the second fetch cue to send to the decode circuit based on the execution result of a comparison instruction.
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Communication from Chinese Patent Office regarding counterpart application.
Communication from Japanese Patent Office re: related application.
Coleman Eric
Harness & Dickey & Pierce P.L.C.
Seiko Epson Corporation
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