Motion video signal processing for recording or reproducing – Local trick play processing – With randomly accessible medium
Reexamination Certificate
1999-05-18
2003-09-09
Tran, Thai (Department: 2615)
Motion video signal processing for recording or reproducing
Local trick play processing
With randomly accessible medium
C360S060000, C380S201000
Reexamination Certificate
active
06618549
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to an information processing apparatus, an information processing method adopted in the apparatus and a presentation medium for presenting the method. More particularly, the present invention relates to an information processing method capable of implementing copy control with a high degree of reliability, an information processing apparatus adopting the method and a presentation medium for presenting the method.
2. Description of the Related Art
FIG. 12
is a diagram showing a typical configuration of an information recording and playback system. As shown in the figure, an IRD (Integrated Recorder/Decoder)
71
, digital-signal recording apparatuses
72
and
73
and a digital-signal playback apparatus
74
are connected to each other by IEEE1394 serial buses
75
.
In the IRD
71
, a receiving circuit
81
receives a satellite broadcast, supplying a transport stream of the received broadcast to a packetizing circuit
82
. The packetizing circuit
82
converts the transport stream supplied thereto into isochronous packets (IPs) conforming to IEEE1394 digital interface standards. The IPs are supplied to the digital-signal recording apparatuses
72
and
73
.
The digital-signal playback apparatus
74
plays back data recorded on a storage-media unit
111
which corresponds to storage-media units
94
and
103
employed in the digital-signal recording apparatuses
72
and
73
respectively. The reproduced data is then decoded by a recording-format decoder
112
. Subsequently, a transport stream output by the recording-format decoder
112
is converted by a packetizing circuit
113
into packets which are then supplied to the digital-signal recording apparatuses
72
and
73
by way of the IEEE1394 serial buses
75
.
The digital-signal recording apparatus
72
has a depacketizing circuit
91
for depacketizing data of the isochronous packets supplied thereto through the IEEE1394 serial bus
75
in order to restore the transport stream which is supplied to a recording-format encoder
93
by way of a CCI (Copy Control Information) rewriting circuit
92
. The depacketizing circuit
91
also supplies the transport stream to a CCI analyzing circuit
95
. The CCI analyzing circuit
95
extracts copy control information (CCI) from the transport stream, analyzes the information and supplies a result of the analysis to a CCI encoder
96
.
The CCI encoder
96
encodes (or changes) CCI supplied thereto into new CCI and outputs the new CCI to the CCI rewriting circuit
92
. The CCI rewriting circuit
92
rewrites CCI included in the transport stream received from the depacketizing circuit
91
with the new CCI received from the CCI encoder
96
, outputting the transport stream to the recording-format encoder
93
. The recording-format encoder
93
encodes the transport stream supplied thereto and records the encoded transport stream into the storage media unit
94
.
A depacketizing circuit
101
and a recording-format encoder
102
employed in the digital-signal recording apparatus
73
carry out the same processing as the depacketizing circuit
91
and the recording-format encoder
93
respectively employed in the digital-signal recording apparatus
72
on data received from the IEEE1394 serial bus
75
, recording a result of the processing into the storage media unit
103
. The digital-signal recording apparatus
73
does not have the CCI analyzing circuit
95
, the CCI encoder
96
and the CCI rewriting circuit
92
employed in the digital-signal recording apparatus
72
. That is to say, the digital-signal recording apparatus
73
functions as a non-cognizant apparatus which is not capable of analyzing CCI recorded in a stream. On the other hand, the digital-signal recording apparatus
72
functions as a cognizant apparatus which is capable of analyzing CCI recorded in a stream.
Next, the operation of the information recording and playback system is explained. An operation to record data received by the IRD
71
is carried out by the digital-signal recording apparatus
73
as follows. When a signal of a predetermined channel is received by the receiving circuit
81
employed in the IRD
71
, the transport stream of the signal is supplied to the packetizing circuit
82
. The packetizing circuit
82
converts the transport stream supplied thereto into isochronous packets which are supplied to the digital-signal recording apparatus
73
through the IEEE1394 serial bus
75
.
In the digital-signal recording apparatus
73
, the depacketizing circuit
101
depacketizes the isochronous packets supplied thereto, outputting the transport stream to the recording-format encoder
102
. The recording-format encoder
102
encodes the transport stream supplied thereto by adopting a predetermined encoding technique, recording the encoded data into the storage media unit
103
.
Data output by the IRD
71
can also be recorded into the digital-signal recording apparatus
72
. In this case, the depacketizing circuit
91
depacketizes the isochronous packets supplied thereto through the IEEE1394 serial bus
75
, supplying the transport stream to the CCI rewriting circuit
92
and the CCI analyzing circuit
95
. The CCI analyzing circuit
95
extracts CCI from the transport stream, analyzes the CCI and supplies a result of the analysis to the CCI encoder
96
. In the CCI encoder
96
, if the CCI is “copy once”, the CCI is converted into “copy prohibited”. If the CCI is “copy free”, the CCI is not changed. If the CCI is “copy prohibited”, the CCI encoder
96
controls the CCI rewriting circuit
92
to prohibit a recording operation.
The CCI rewriting circuit
92
receives CCI obtained as a result of encoding from the CCI encoder
96
. If the CCI received from the CCI encoder
96
is “copy free” or “copy prohibited”, the CCI rewriting circuit
92
rewrites the CCI included in the transport stream received from the depacketizing circuit
91
with the CCI received from the CCI encoder
96
, outputting the rewritten transport stream to the recording-format encoder
93
. The recording-format encoder
93
encodes the transport stream supplied thereto, recording the encoded data into the storage media unit
94
.
As described above, data output by the IRD
71
is recorded. It should be noted that data played back by the digital-signal playback apparatus
74
can also be recorded. In this case, the digital-signal playback apparatus
74
plays back data recorded on the storage-media unit
111
. The reproduced data is then decoded by the recording-format decoder
112
. Subsequently, a transport stream output by the recording-format decoder
112
is converted by the packetizing circuit
113
into isochronous packets which are then supplied to the digital-signal recording apparatuses
72
and
73
by way the IEEE1394 serial buses
75
. Then, a recording operation is carried out in the same way as what is described above.
A transport stream output by the receiving circuit
81
conforms to the MPEG
2
systems (ISO/IEC13818-1). In the transport stream, video and audio streams are multiplexed in transport-packet units each having a length of 188 bytes. Assume that the digital-signal recording apparatus
72
is a DVCR (Digital Video Cassette Recorder) for consumer use. In this case, the depacketizing circuit
91
outputs data obtained as a result of addition of 3-byte TSP_extra_header to the head of 187 bytes as shown in FIG.
13
. The 187 bytes are the bytes of a transport packet of the transport stream conforming to the MPEG
2
systems excluding a byte of the sync_byte at the head of the transport packet. The syntax of TSP_extra_header has a configuration shown in FIG.
14
. As shown in the figure, TSP_extra_header includes 21-bit time_stamp_counter which represents a planned arrival time of the first bit of the first byte of a transport packet at an input of a T-STD (Transport Stream System Target Decoder) or a smoothing buffer defined in the ISO/IEC 13818-1 (MPEG
2
systems).
In the DVCR, a clock having a frequency of 27 MHz is locked in a PCR
Fujinami Yasushi
Kato Motoki
Kessler Gordon
Tran Thai
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