Information processing apparatus having dual buffers for transmi

Details Information processing apparatus having dual buffers for transmi Information processing apparatus having dual buffers for transmi

1995-01-12

1997-04-29

Lim, Krisna

Boots, shoes, and leggings

3642318, 36424341, 36424342, 39518314, G06F 938

Patent

active

056257856

ABSTRACT:
An information processing apparatus has an instruction execution unit (IEU), a counter, first and second FIFO buffers, and a selector. The IEU executes instructions. The counter traces an order of execution of the instructions executed by the IEU and stores the order of execution as an order data. The first FIFO buffer stores a branch source address data obtained by a branch instruction together with the order data. The second FIFO buffer stores a content of a memory obtained by a memory access instruction or push data obtained by a stack push instruction together with the order data. The selector selects one of the data stored in the first and second FIFO buffers and provides it to an external device. The selector selects the first FIFO buffer prior to the second FIFO buffer as long as the first FIFO buffer has the branch source address data stored therein.

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Sohi; Instruction Issue Logic for High-Performance, Interruptible, Multiple Functional Unit, pipelined computers; pp. 349-359.

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