Information processing apparatus having an instruction prefetch

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G06F 922

Patent

active

047470453

ABSTRACT:
An information processing apparatus with an instruction prefetch unit is disclosed, in which a CPU operation can be stopped at a desired address in response to a break signal. The instruction prefetch unit has an instruction prefetch circuit storing an instruction and an indication register storing the break signal. A read operation and a write operation of the indication register are executed together with those of the instruction prefetch circuit. Thus, a break point can be set a desired address by using the indication register, and the break operation can be correctly preformed without the need for complex hardware.

REFERENCES:
patent: 3401376 (1968-09-01), Barnes et al.
patent: 3551895 (1970-12-01), Driscoll
patent: 3577190 (1971-05-01), Cocke et al.
patent: 3764988 (1973-10-01), Onishi
patent: 4106090 (1978-08-01), Erickson et al.
patent: 4298933 (1981-11-01), Shimokawa et al.

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