Electrical computers and digital processing systems: processing – Processing architecture – Microprocessor or multichip or multimodule processor having...
Reexamination Certificate
1999-02-16
2001-06-19
Pan, Daniel H. (Department: 2183)
Electrical computers and digital processing systems: processing
Processing architecture
Microprocessor or multichip or multimodule processor having...
C712S221000, C712S009000
Reexamination Certificate
active
06249858
ABSTRACT:
BACKGROUND OF THE INVENTION
1 Technical Field of the Invention
The present invention relates generally to an improvement on an information processing apparatus such as a microcomputer which has a CPU and an auxiliary arithmetic unit such as a coprocessor for achieving high-speed operations.
2 Background Art
Computer systems are known in the art which perform a pipelined operation in which a plurality of instructions are executed in a plurality of parallel steps concurrently and in an overlapped fashion. Specifically, a CPU divides the process of executing each instruction into five stages: IF (instruction fetch), ID (instruction decode), EX (execution), MA (memory access), and WB (write back). The IF stage is a fetch operation which reads an instruction out of a peripheral memory such as a ROM or a RAM. The ID stage is a decode operation in which the instruction is decoded to indicate an operation to be carried out. The EX stage is an execution operation in which the decoded operation is carried out. The MA stage involves a memory access to the peripheral memory for transmission of data between the memory and the CPU. The WB stage is a writing operation to write data in the peripheral memory.
In recent years, microcomputers used in machine control are required to achieve a high-speed operation of the CPU and improvement of ability to process digital signals.
While the high-speed operation of the CPU may be realized to some extent by the pipelined operation as described above, the improvement of ability to process digital signals requires either of the following two methods.
The first is to install a DSP (Digital Signal Processor) in the microcomputer independent of the CPU.
The second is to connect a coprocessor designed to perform special arithmetic operations such as calculation of logarithm or the sum of products which the CPU cannot execute at high speeds with the CPU using a bus for allowing the coprocessor to perform the special arithmetic operations in response to a command issued by the CPU.
The former is not practical because the DSP is bulky, and it is difficult to reduce the size of an LSI.
The latter encounters a difficulty in executing operations concurrently in the CPU and the coprocessor. Specifically, even if the CPU and the coprocessor gain access to different memories during operations, data from the CPU and the coprocessor are transmitted through the same bus, thus resulting in difficulty in proper access to the memories. The latter is, thus, useful in speeding the operation of the CPU, but has a limitation of improvement of ability to process digital signals.
SUMMARY OF THE INVENTION
It is therefore a principal object of the present invention to avoid the disadvantages of the prior art.
It is another object of the present invention to provide an information processing apparatus which has a CPU and a coprocessor and which is capable of executing instructions at high speeds.
According to one aspect of the invention, there is provided an information processing apparatus which comprises: (a) a central processing unit; (b) an auxiliary arithmetic unit connected to the central processing unit through a bus, the auxiliary arithmetic unit being responsive to a start command issued by the central processing unit to execute a given operation; and (c) a switch disposed in the bus to selectively establishing and blocking communication between the central processing unit and the auxiliary arithmetic unit
4
. The blocking of the communication allows the central processing unit and the auxiliary arithmetic unit to operate in parallel to each other.
In the preferred mode of the invention, the auxiliary arithmetic unit has memory locations one for each of preselected operations. When data is written by the central processing unit into one of the memory locations, the auxiliary arithmetic unit executes a corresponding one of the preselected operations on the data written into the one of the memory locations and outputs a signal to the switch to block the communication between the central processing unit and the auxiliary arithmetic unit.
A second bus is further provided which is isolated from the bus and which connects with the auxiliary arithmetic unit. A memory is provided which connects with the second bus and which stores therein data on constants used in the operations executed by the auxiliary arithmetic unit.
According to another aspect of the invention, there is provided an information processing apparatus which comprises: (a) a central processing unit; (b) an auxiliary arithmetic unit connected to the central processing unit through a bus; (c) a register installed in the auxiliary arithmetic unit which has memory locations one for each of preselected operations, when data is written by the central processing unit into one of the memory locations, the auxiliary arithmetic unit executing a corresponding one of the preselected operations on the data written into the one of the memory locations; and (d) a dual port memory having two pairs of ports through which data is written into and read out of the dual port memroy, one of each pair of ports being connected to the bus and the other being connected to the auxiliary arithmetic unit through a second bus for allowing the CPU and the auxiliary arithmetic unit to operate in parallel to each other.
In the preferred mode of the invention, a third bus is futher provided which is isolated from the bus and the second bus and which connects with the auxiliary arithmetic unit . A memory is provided which connects with the third bus and which stores therein data on constants used in the operations executed by the auxiliary arithmetic unit.
REFERENCES:
patent: 3593316 (1971-07-01), Frieband
patent: 3909800 (1975-09-01), Recks et al.
patent: 4908748 (1990-03-01), Pathak et al.
patent: 0 299 075 (1989-01-01), None
patent: 0 540 175 (1993-05-01), None
patent: 1-255037 (1989-10-01), None
patent: 4-262450 (1992-09-01), None
Electronics, Mar. 1997; pp. 5-7 (with english abstract).
Kiuchi, et al., “RISC Microcomputer SH-DSP for Replacement with DSP”. Nikkei Electronics, Jul. 1996, pp. 147-161 (with english abstract).
BEIMS: “The MC68020 32-bit MPU: Opening new doors” WESCON Proceedings vol. 29, No. 1/4, Nov. 19-22, 1985, pp. 1-17, XP000211744 San Francisco, US* p. 7, right-hand column*.
Ertem M C: “A Reconfigurable Co-Processor for Microprocessor Systems” Proceedings of the Southeast Conference, Tampa, Apr. 5-8, 1987, vol. 1, Apr. 5, 1987, pp. 225-228, XP000212298 Institute of Electrical and Electronics Engineers.
Fukumoto Harutsugu
Hayakawa Hiroshi
Ishihara Hideaki
Tanaka Hiroaki
Denso Corporation
Pan Daniel H.
Pillsbury & Winthrop LLP
LandOfFree
Information processing apparatus having a CPU and an... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Information processing apparatus having a CPU and an..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Information processing apparatus having a CPU and an... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2449558