Patent
1995-09-29
1998-08-04
Ellis, Richard L.
395598, G06F 132
Patent
active
057908745
ABSTRACT:
An instruction sequence optimization apparatus optimizes programs used in an information processing system that includes a program memory for storing programs, and a processing unit for fetching the programs from the program memory via an instruction bus. The apparatus includes an instruction sequence analyzing unit for analyzing mutual dependence relations between respective instructions constituting the program, and an instruction sequence modifying unit for modifying sequences of the instructions insofar as the mutual dependence relations analyzed by the instruction sequence analyzing unit are not influenced, to thus reduce Hamming distances between bit sequences appearing on the instruction bus when the instructions are transferred from the program memory to the processing unit.
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Su et al., Saving Power in the Control Path of Embedded Processors, IEEE Design & Test of Computers, pp. 24-30, Winter 1994.
Printout from Instn. Electrical Engineers substantiating dates for IEEE articles authored by Su et al.
Su et al., "Low Power Architecture Design and Compilation Techniques for High-Performance Processors", IEEE, pp. 489-498, (1994).
Ide Nobuhiro
Takano Hiroyuki
Yoshida Takeshi
Ellis Richard L.
Kabushiki Kaisha Toshiba
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