Computer graphics processing and selective visual display system – Computer graphic processing system – Plural graphics processors
Reexamination Certificate
1997-11-25
2002-05-14
Tung, Kee M. (Department: 2671)
Computer graphics processing and selective visual display system
Computer graphic processing system
Plural graphics processors
C345S506000, C345S419000, C345S582000
Reexamination Certificate
active
06388671
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to information processing apparatuses and information processing methods, and more particularly to an information processing apparatus and an information processing method for performing information processing of three-dimensional graphics.
Recently, development of semiconductor integrated circuits for realizing a multimedia information processing apparatus is actively undertaken. In the field of multimedia, it is required that various types of data including movie data, audio data, CG data or the like be handled by a single apparatus. With the development of semiconductor integrated circuits, a single element nowadays realizes the function hitherto realized by a plurality of semiconductor integrated circuits. However, it is quite difficult to handle an extensive variety of data, or to incorporate all the necessary functions in a semiconductor integrated circuit having a limited scale.
Hence, a general practice is that a desired function is realized by writing a program for achieving a variety of combinations of basic logic operation functions that the semiconductor integrated circuit is equipped with, in accordance with a stored program control method (a method whereby a necessary logic function is realized by a generally used microprogram).
In the above described method, the logic function equal to the desired function can be realized as a whole. However, since the number of instructions combined varies, there are cases in which the process cannot be completed in a predetermined period of time. From the perspective of the uniform execution of processes, realization of process functions (algorithms) in each and every field by a set of logic functions (instruction sets) does not actually meet the requirement.
An approach to resolve this problem is to define a frequently used logic function that serves a purpose as a single instruction and an optimization is performed so that the defined function can be executed at a high speed using hardware.
Here, it is noted that, if a relatively simple process and a relative complex auxiliary process for facilitating the process are executed in combination, a high-speed execution of three-dimensional graphics processing is effectively achieved. For this purpose, it is necessary to employ a processing apparatus where the process in accordance with the stored program method and the process using hardware are combined.
2. Description of the Prior Art
FIG. 1
is a block diagram of a conventional information processing apparatus. A host computer
41
is connected to a display device
44
via a graphic processing part
42
and a frame memory
43
. three-dimensional image data produced in the host computer
41
is developed into 2-D data by the graphic processing part
42
, stored in the frame memory
43
and displayed in the display device
44
.
The graphic processing part
42
comprises a DDA (linear interpolation process) part
42
a
which interpolates data on the basis of data representing vertices of a polygon and transferred from the host computer
41
; a texture process part
42
b
for pasting a pattern to the polygon; a rendering condition determination part
42
c
for making a determination as to whether or the data should be used in rendering on the basis of the data function or the like; and a blender part
42
d
for performing a blending process where colors of adjacent pixels are blended. The process of each part is executed according to a pipeline process scheme.
The data processed by the graphic processing part
42
is developed in the frame memory
43
. The display device
44
displays image that corresponds to the data developed in the frame memory
43
.
Under the pipeline process scheme, the graphic processing part
42
is so constructed as to execute only a process for which it is designed. Correction of data required for the process in the graphic processing part
42
is executed in the host computer
41
. For example, an auxiliary process including matching of the coordinates of the polygon to be rendered to the coordinates of the pixels on the display, is executed in the host computer
41
.
In the conventional information processing apparatus, calculation of endpoints between the vertices of the polygon is executed by the host computer characterized by its flexibility in the processing, because the calculation needs a complex process including the correction of data. Therefore, the load imposed on the host computer becomes large. In addition to that, there is a problem in that changing of viewpoints cannot be performed at a high speed because the data must be read from the host computer. Hence, efficient execution of three-dimensional image process is impossible.
SUMMARY OF THE INVENTION
Accordingly, an object of the present invention is to provide a novel and useful information processing apparatus and an information processing method in which the aforementioned problems are eliminated.
Another and more specific object of the present invention is to provide an information processing apparatus and an information processing method in which the information processing can be done efficiently.
The aforementioned objects of can be achieved by an information processing apparatus which executes a process according to input information, the information processing apparatus comprising:
first information processing means for executing a process set exclusively with respect to the input information; and
second information processing means which is capable of executing a process parallel with the first information processing means, for executing a process according to process-related information with respect to the input information. According to the information processing apparatus of the present invention, while the first information processing means is executing input information processes to which it is dedicated, an auxiliary process is performed by the second information processing means in a parallel manner. Thus, it is possible to process information at a high speed.
In a preferred embodiment, the second information processing means has process-related information storing means for storing the process-related information. According to this aspect, it is possible to control the process executed by the second information processing means and information input/output of the second information processing means. Therefore, it is possible to prevent a contention for information from occurring between the first information processing means and the second information processing means. Thus, it is possible to execute information process efficiently.
In another preferred embodiment, the second information processing means has communicating means for communicating with a host system. According to this aspect, it is possible to supply information to the second information processing means from the master system irrespective of the process in the first information processing means. Therefore, the process in the second information processing means is conducted smoothly and efficiently, thus improving the speed of the process.
In another preferred embodiment, the information processing means comprises: a first operation part processing information in accordance with the process-related information; and a second operation part which processes information in accordance with the process-related information and is capable of executing a process parallel with the first operation part. According to this aspect, the first operation part processes information in accordance with the process-related information and the second operation part controls the operation of the first information processing means. In this way, the first information processing means can be controlled to execute the process in an optimal manner, thus enabling the information process to be executed efficiently.
In another preferred embodiment, the second information processing means has shared storing means accessible both from the first operation part and from the second operation part. According t
Otsuka Tatsushi
Sasaki Shigeru
Tatematsu Ritsuko
Yoshizawa Hideki
Fujitsu Limited
Staas & Halsey , LLP
Tung Kee M.
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