Information processing apparatus and information processing meth

Electrical computers and digital processing systems: processing – Processing architecture – Microprocessor or multichip or multimodule processor having...

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712227, 345522, 345327, 345334, G06F 940, G06F 314

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active

061192171

ABSTRACT:
Priorities are assigned to a plurality of central processing units (CPUs) and the CPUs transfer their respective display lists of drawing instructions to a drawing unit on a priority basis. When a master CPU (Geometry Subsystem 0) is creating a display list (List #0-1) and a drawing unit (a rendering system) is in an idle state, a right to make an access to the drawing unit is handed over to a slave CPU (Geometry Subsystem 1), enabling the slave CPU to supply a display list (List 1-1) created thereby, if any, to the drawing unit. Receiving the display list (List #1-1), the drawing unit starts drawing processing in accordance with List #1-1. As the master CPU completes the creation of the display list (List #0-1), the slave CPU returns the right to make an access to the drawing unit to the master CPU, enabling the master CPU to supply List #0-1 to the drawing unit. Receiving the display list (List #0-1), the drawing unit starts drawing processing in accordance with List #0-1. Thereafter, when the master CPU is creating a display list and the drawing unit is in an idle state, a right to make an access to the drawing unit is handed over to the slave CPU (Geometry Subsystem 1), enabling the slave CPU to supply another display list created thereby, if any, to the drawing unit in the same way.

REFERENCES:
patent: 5239654 (1993-08-01), Ing-Simmons et al.
patent: 5706478 (1998-01-01), Dye

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