Electrical computers and digital processing systems: processing – Processing architecture – Microprocessor or multichip or multimodule processor having...
Reexamination Certificate
2000-07-11
2001-10-16
Pan, Daniel H. (Department: 2183)
Electrical computers and digital processing systems: processing
Processing architecture
Microprocessor or multichip or multimodule processor having...
C712S034000, C712S035000, C712S211000, C710S244000, C710S241000, C711S112000, C345S503000, C345S215000, C345S522000, C345S520000, C345S215000
Reexamination Certificate
active
06304952
ABSTRACT:
BACKGROUND OF THE INVENTION
In general, the present invention relates to an information processing apparatus and an information processing method. More particularly, the present invention relates to an information processing apparatus and an information processing method wherein and whereby typically a plurality of CPUs generate their respective instructions concurrently and transfer the generated instructions to a drawing unit in accordance with priorities assigned to the CPUs so as to allow drawing processing to be carried out by the drawing unit with a high degree of efficiency.
With larger scales of integration of LSIs achieved in recent years, a plurality of identical circuits can be laid out in parallel in one LSI, allowing the speed of processing carried out thereby to be increased. By the way, a video game system manufactured in recent years comprises a central processing unit (CPU) and a drawing unit. Receiving data representing a polygon to be displayed from a controller, the CPU carries out 2-dimensional or 3-dimensional coordinate transformation on the data and creates a list of drawing instructions used for drawing the polygon on a 2-dimensional frame buffer. The CPU then transfers the list which is referred to hereafter as a display list to the drawing unit for drawing the polygon in accordance with the display list.
However, effects of improving the throughput of a processing system by adopting a parallel processing technique are reaped more effectively for a system wherein a number of simple operations are carried out repeatedly as is the case with the drawing unit. As a consequence, the speed of processing executed by the CPU is relatively low in comparison with a parallel processing drawing unit produced in recent years. In addition, in order to reduce the amount of 3-dimensional model data, it is necessary to generate a complex graphic such as a curved surface from few pieces of vertex data (control points) each time a drawing operation is carried out. It is the CPU that has to bear the load of processing to generate such a complex graphic. As a result, there is raised a problem that the drawing processing can not be carried out with a high degree of efficiency.
OBJECT AND SUMMARY OF THE INVENTION
Addressing the problems described above, it is an object of the present invention to provide an information processing apparatus and an information processing method that allow data to be processed with a high degree of efficiency by assigning priorities to a plurality of CPUs, letting the CPUs operate concurrently and processing display lists generated by the CPUs on a priority basis starting with a display list generated by a CPU having a highest priority.
An information processing apparatus according to claim
1
is characterized in that said apparatus comprises:
a first generation means for carrying out processing to generate a first instruction;
a second generation means for carrying out processing to generate a second instruction;
an execution means for executing said first and second instructions by switching from said first instruction to said second instruction and vice versa with predetermined timing;
a first transfer means for transferring said first instruction to said execution means; and
a second transfer means for transferring said second instruction to said execution means,
wherein, when said first generation means is in the course of processing and said execution means is in a wait state, said second transfer means supplies said second instruction, if any, to said execution means and, receiving said second instruction, said execution means executes said second instruction.
An information processing method according to claim
5
is characterized in that, when a first generation means is in the course of processing and an execution means is in a wait state, a second transfer means supplies a second instruction, if any, to said execution means and, receiving said second instruction, said execution means executes said second instruction.
In the information processing apparatus according to claim
1
wherein
a first generation means carries out processing to generate a first instruction;
a second generation means carries out processing to generate a second instruction;
an execution means executes said first and second instructions by switching from said first instruction to said second instruction and vice versa with predetermined timing;
a first transfer means transfers said first instruction to said execution means; and
a second transfer means transfers said second instruction to said execution means,
when said first generation means is in the course of processing and said execution means is in a wait state, said second transfer means supplies said second instruction, if any, to said execution means and, receiving said second instruction, said execution means executes said second instruction.
With the information processing method according to claim
5
, when a first generation means is in the course of processing and an execution means is in a wait state, a second transfer means supplies a second instruction, if any, to said execution means and, receiving said second instruction, said execution means executes said second instruction.
The above and other objects, features and advantages of the present invention will become more apparent from the following detailed description when taken in conjunction with the accompanying drawings which illustrate a preferred embodiment of the present invention by way of examples.
REFERENCES:
patent: 4631674 (1986-12-01), Blandy
patent: 5101341 (1992-03-01), Circello et al.
patent: 5335322 (1994-08-01), Mattison
patent: 5787241 (1998-07-01), Henry et al.
patent: 6119217 (2000-09-01), Suzuoki
patent: 0 598 231 A2 (1994-05-01), None
Communication from European Patent Office re search report—Documents Considered to be Relevant, (Sep. 30, 1999), Application No. EP93116856.
Fulwider Patton Lee & Utecht LLP
Pan Daniel H.
Sony Computer Entertainment Inc.
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