Information processing apparatus

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364DIG1, G06F 1206

Patent

active

051796856

ABSTRACT:
An information processing apparatus for managing a storage such as a register file divided into a plurality of register banks. A register bank pointer is provided for each register bank in the register file so as to link the register bank to another optional register bank. The activation records for each of a plurality of tasks are allocated to the corresponding register banks in the register file. The necessary number of register banks for the allocation of the activation records for each task are linked together. The number of register banks linked together or released from the linking is changed with the increase and decrease of the number of activation records to be allocated for each task.

REFERENCES:
patent: 4734852 (1988-03-01), Johnson et al.
patent: 4766566 (1988-08-01), Chuang
patent: 4777588 (1988-10-01), Case et al.
patent: 4833640 (1989-05-01), Baba
M. G. H. Katevenis "Reduced Instruction Set Computer Architecture for VLSI", The MIT Press, 1985, pp. 52-64.

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