Electricity: electrical systems and devices – Housing or mounting assemblies with diverse electrical... – For electronic systems and devices
Reexamination Certificate
1998-03-03
2001-01-23
Gandhi, Jayprakash N. (Department: 2841)
Electricity: electrical systems and devices
Housing or mounting assemblies with diverse electrical...
For electronic systems and devices
C361S748000, C361S753000, C361S792000, C361S796000, C174S255000, C174S262000, C174S264000, C428S209000, C428S210000, C428S212000, C428S321300, C428S901000, C029S852000, C216S018000, C427S097100
Reexamination Certificate
active
06178093
ABSTRACT:
FIELD OF THE INVENTION
This invention relates to high density computer systems using circuit board assemblies and manufacture of circuit board assemblies in which surface mount components and pin in hole components are attached to circuitized substrates by soldering component terminals into plated through holes and to connection pads on the substrate. More particularly this invention relates to methods for forming electrically conductive vias between buried wiring layers; forming multiple very fine external wiring layers; and organic materials made conductive by filling with conductive particles.
BACKGROUND
The following background is for convenience of those skilled in the art and for incorporating the listed citations by reference. The following background information is not an assertion that a search has been made, or that the following citations are analogous art, or that any of the following citations are pertinent or the only pertinent art that exists, or that any of the following citations are prior art.
The continued introduction of very high I/O and very high density surface mount components especially 0.2-0.4 mm gull wing leaded components, 40 mil ball grid array BGA modules, as well as the direct connection flip chips to circuit boards, has resulted in a need for very high density conductor fan out at these components. At the same time, decrease in the size of plated through holes PTHs which interconnect between wiring layers, has not kept up with these requirements for fan out. PTHs require substantial surface area which can not be easily reduced because seeding and plating require circulation of fluids in the holes. Reducing the size of connections between wiring layers has become critical for continued increase in circuit board density.
For such high density surface mount components, solder volummes are a critical process variable, but when components are attached to PTHs even those filled with solder, the solder volume between the terminals of the components and the PTHs can not easily be controlled.
Those skilled in the art are directed to the following references U.S. Pat. No. 4,967,314 to Higgins, III suggests filling via interconnect holes with a conductive epoxy. U.S. Pat. No. 3,163,588 to Shortt suggests stripable frisket, seeding and electroplating.
Face Protection of Printed Circuit Boards
by McDermott in
IBM Technical Disclosure Bulletin
Vol. 11 No. 7 December 1968 describes peelable coverings and pressing resin into plated through holes.
Printed Circuit Base
by Marshall in
IBM TDB
Vol. 10, No. 5, October 1967, describes a sensitizing material. U.S. Pat. No. 4,590,539 to Sanjana discloses epoxies, fillers, curing agents, and catalysts. U.S. Pat. No. 4,791,248 to Oldenettel suggests peel apart coverings, filling holes with resin, and planing off resin nubs. U.S. Pat. No. 4,893,440 to Shirahata discloses buried vias and electroconductive organic based paste. U.S. Pat. No. 4,964,948 to Reed suggests methods for seeding a substrate for electroplating. U.S. Pat. Nos. 4,991,060 and 5,028,743 to Kawakami suggests filling through holes with electroconductive paste and buried vias. U.S. Pat. No. 5,065,227 to Frankeny suggests electrically conductive paste filling a via hole. U.S. Pat. No. 5,243,142 to Ishikawa discloses hole fill. U.S. Pat. No. 5,271,156 to Isasaka discloses manufacturing methods for multi-layer ceramic substrates including filling holes punched in green sheets with conductive paste. U.S. Pat. No. 5,319,159 to Watanabe suggests method of manufacturing a double sided printed wiring boards with resin filled PTHs. Japanese application 2-045998 suggests filling through holes with electroconductive thermosetting paste. Japanese application 2-184626 to Honda suggests using a novolac epoxy resin such as cresol novolac epoxy resin for a circuit board. U.S. Pat. No. 5,346,750 to Hatakeyama suggests a method to prevent bleed out of paste from a filled via. U.S. Pat. Nos. 4,354,895 to Ellis, 5,057,372 to Imfeld, and 5,262,247 to Kajiwara suggests a metal foil with a peel apart protective layer. U.S. Pat. Nos. 5200026 to Okabe and 5,266,446 to Chang suggest processes for forming thin film structures on substrates. U.S. Pat. Nos. 4,940,651 to Brown, 5,026,624 to Day, 5,070,002 to Leech, 5,300,402 to Card, 5,427,895 to Magnuson, and 5,439,779 to Day discuss photoresists. U.S. Pat. Nos. 4,127,699 to Aumiller, 4,210,704 to Chandross, 4,731,503 to Kitanishi, 4,747,968 to Gilleo, 4,822,523 to Prud'Homme, 4,880,570 to Sanborn, 4,904,414 to Peltz, 4,999,136 to Su, 5,082,595 to Glackin, 5,220,724 to Gerstner, and 5,463,190 to Carson suggest various electrically isotopically conductive organic materials.
New Avenue for Microvias
in
Electronic Engineering Times
Mar. 18, 1996. p. 68 reports that Prolinx Labs Corp of San Jose, Calif. has developed an additive technology for blind and buried vias filled with conductive material. The proceeding citations are hereby incorporated in whole by reference.
SUMMARY OF THE INVENTION
In the invention of Applicants, holes in a first substrate structure are filled with an organic based conductive material and additional substrate layers are laminated to the substrate without causing the organic material to bleed out between the first substrate and the additional substrates during lamination. Also, metal may be plated over the organic material prior to laminating additional substrates onto the first substrate. The organic material may be filled with thermoconductive dielectric particles for better thermal performance or filled with electroconductive particles to provide conductive holes. Conductive vias in the additional substrates may be plated to connect to the conductive material in the filled holes. A cresol-novolac epoxy precursor may be filled with 70-80% by weight electroconductive particles such as copper and/or silver powder and cured and may subsequently be plated with copper. This allows conductive vias such as PTHs filled with electroconductive or thermoconductive material or holes filled with electroconductive material to be buried in the substrate and avoids excessive surface area from being utilized for vias between internal wiring layers. Also, the exterior substrate may be provided with photo-vias which require much less surface area than PTH's. The invention allows decreased wiring lengths between components so that a computer system utilizing such circuit boards will operate at a higher speed.
The invention includes a process for producing the circuit boards of the invention. In the process a peel apart structure including a copper foil and removable film is positioned with the copper foil in contact with the substrate and is laminated to a substrate. Then holes are formed in the substrate through the peel apart structure. Also, a sacrificial carrier is coated with an organic resin filled with conductive particles and then partially cured to form a carrier structure. The partially cured resin is positioned between the removable film and the sacrificial carrier and heat and pressure is applied to force the partially cured filler material into the holes with the peel apart structure acting as a mask. Finally, the removable film, the sacrificial carrier, and the conductive material remaining therebetween are peeled away leaving the copper foil laminated to the substrate.
The surface of the filler material is flattened by abrasion to the same level as the copper foil and the surface of the filler material is plated with copper. The copper foil is patterned to form a wiring layer then a dielectric photoresist is laminated to the wiring layer. Since the filler material is partially cured and covered by electroplated copper it does not bleed from the holes in between the wiring layer and the photoresist. Conductive photo-vias which are connected to the wiring layer, are formed through the photoresist and copper is deposited on the photoresist and patterned to form another wiring layer over the photoresist and also connected to the conductive vias.
The invention also includes the structures that resu
Bhatt Anilkumar Chinuprasad
Glatzel Donald Herman
Markovich Voya Rista
Moring Allen F.
Papathomas Kostas
Fraley Lawrence R.
Gandhi Jayprakash N.
International Business Machines - Corporation
Pollock Vande Sande & Amernick
Vigushin John B.
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