Patent
1996-10-07
1999-02-02
Heckler, Thomas M.
G06F 106
Patent
active
058676945
ABSTRACT:
An information handling system, having a programmable clocking system for clocking data in and out of a processor, includes a processor, having one or more buses connected thereto, wherein a processor clock, and a clock for each of the buses connected to the processor, may be operating at different clock rates relative to each other, the programmable clocking circuit for generating bus clock signals with predetermined cycle skew eliminates the need to distribute separate clock signals across the processor chip. The clock generation circuit uses signals available on the processor integrated circuit for functional operation and tests. Further, flush and hold signals control predetermined latches in the clock generator circuit.
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patent: 4845437 (1989-07-01), Mansor et al.
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patent: 5564027 (1996-10-01), Bui et al.
patent: 5588004 (1996-12-01), Suzuki et al.
patent: 5600824 (1997-02-01), Williams et al.
Billings Richard Vincent
Jaber Tafal Kamel
Lattimore George McNell
Reese Robert James
England Anthony V. S.
Heckler Thomas M.
International Business Machines - Corporation
Kordzik Kelly K.
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