Dynamic information storage or retrieval – Binary pulse train information signal – Including sampling or a/d converting
Reexamination Certificate
2000-12-22
2003-12-30
Tran, Thang V. (Department: 2653)
Dynamic information storage or retrieval
Binary pulse train information signal
Including sampling or a/d converting
C369S124070, C369S047180
Reexamination Certificate
active
06671244
ABSTRACT:
BACKGROUND OF THE INVENTION
This invention relates to an apparatus for reproducing information which have been recorded with high density and, in particular, to an apparatus for improving a follow-up performance and an information detecting performance.
Recently, it is required to process a large quantity of information with the rapid development in multi-media. Following this, requirements are also being made for a storage device having a large capacity for recording the information.
In order to meet this requirement, a recording density should be enhanced to increase a recording capacity of an optical disk devise or a HDD device as well as to reduce an error rate and to ensure the reliability.
Meanwhile, a reproducing system called “PRML (Partial Response Maximum Likelihood)” is popularly utilized for a file device because this system ensures a high reproducing performance for a high-density recording/reproducing waveform having a low resolution.
Herein, it is to be noted that the PRML system is structured by combining a partial response waveform equalization with a maximum likelihood detection.
It is well known to detect the maximum likelihood after correcting the reproducing waveform by equalizing the waveform in order to maximize a characteristic to a maximum likelihood detector considering a reproducing channel into account.
The PRML system is disclosed in, for example, a preprints of ITE '94:1994 ITE Annual Convention, pages 287-288, titled “A PRML System on the Optical Video Disk Recorder” by S. Itoi, et al.
When the information recorded with the high density is reproduced in the optical disk and the magnetic disk, inter-symbol interference becomes large and the reproducing amplitude will be lowered.
Followingly, SNR (signal to noise ratio) becomes small in the magnetic disk while CNR (carrier to noise ratio) of a high frequency component of a readout signal becomes small in the optical disk. As a result, an error rate of a detected information will inevitably be increased.
In the maximum likelihood system, the information is detected by utilizing the characteristic of the reproducing channel having the predetermined state transfer.
The information is selected so as to minimize a root mean square of an error among all time series patterns considered from the characteristic of the reproducing channel for amplitude information series having the quantum bit number of about 8 bits inputted to the detector.
Thereby the information can be detected with a lower error rate even when the SNR or CNR is small.
It is difficult to perform the above-mentioned process with an actual circuit from the viewpoints concerning a circuit scale and an operation speed. Normally the above-mentioned process is realized by gradually selecting paths using algorithms called “Viterbi algorithms”. Herein, the Viterbi-algorithms are disclosed in a paper, for example, IEEE Transaction on Communications Technology, VOL. COM-19, No. 5, October 1971, pages 751-772.
In this case, the Viterbi detector and a digital circuit group connected afterward are synchronous circuits and therefore require a synchronous clock signal.
Generally, the clock signal is produced from the readout signal itself. However, the readout signal of the disk device slightly changes in accordance with the rotation jitter of a spindle or disk tilts A clock extracting circuit called PLL (Phase Locked Loop) is required in order to deal with the above-mentioned change.
In the case where the Viterbi detector is used, a stationary phase error is generated in the structure of the conventional analog PLL circuit and the PRML detector, and the error rate raises. In this viewpoint, a phase synchronous loop is generally structured by carrying out a phase comparison using a sample data (namely, a digital data) after an analog-digital conversion (A/D conversion).
For example, the above-mentioned PLL circuit is disclosed in Japanese Unexamined patent Publication (JP-A) No. Hei. 8-321140 or Japanese Unexamined patent Publication (JP-A) No. Hei. 9-204740.
In the PLL circuit disclosed in the above Japanese Unexamined Patent Publication (JP-A) No. Hei. 8-321140, an output of a loop filter (LPF; low path filter) is converted into an analog signal by the use of a D/A converter (DAC), and is supplied to a voltage control oscillator (VCO) of an analog system in order to generate a PLL clock.
In this event, it is difficult to structure the PLL circuit having the same grade of the performance because the analog VCO circuit has a large characteristic difference.
In contrast, disclosure has been made about a reproducing method in which an A/D conversion is carried out by the use of a system clock that is not synchronized with a channel clock of a readout signal, and a sample series having a desired phase is re-generated by an interpolation circuit.
By using the above-mentioned method, an entire reproducing system including the PLL circuit can be digitized.
Further, suggestion has been made about an automatic equalizing method or an adaptive equalizing method as techniques for enhancing a detecting performance by adaptively correcting deterioration of the signal with time.
For example, disclosure has been made about an continuous-type of adaptive equalizing algorithms in a paper by Hirosi Inose and Hiroshi Miyagawa, titled “Improvement of PCM communication” pp. 148-184, and in particular, “Zero Forcing method”, “Mean Square method” and “Modified Zero Forcing method” are generally used. Such an adaptive equalizing technique has an advantageous effect because an initial adjustment of the device is not necessary.
The conventional type of a circuit for realizing the adaptive equalization includes a plurality of multipliers and integrators which as a result leads to a serious problem from the viewpoint of a circuit scale.
However, this problem has been almost resolved with the recent development of the semiconductor processing technique.
As mentioned above, the readout signal recorded with the high density is deteriorated in SNR by the affect of the inter-symbol interference. Consequently, more excellent follow-up performance can be obtained in PLL by correcting the frequency characteristic by the equalizer.
Two kinds of structures are known depending upon the arrangement of the equalizer, each of which has both the advantages and disadvantages.
A first structure is the most generally used structure, Namely, after the equalization is carried out by the use of the analog equalizer, the A/D conversion is performed to conduct the PLL operation. In first structure, it is difficult to automatically adjust the equalizing characteristic.
Therefore, the first structure can not cope with the characteristic change of the readout signal caused by the deterioration of the head, the mechanism, and the medium with time and the operating environment condition. A wide margin should preliminarily be assigned for the signal detecting system in advance.
In contrast, a second structure is illustrated in FIG.
1
. Specifically, a digital equalizer
2
is inserted between an output of an A/D converter
1
given with a readout signal and a PLL circuit (including a phase comparator
41
, LPF
42
, DAC
44
, and VCO
45
) in the adaptive equalizer.
The adaptive equalizer is provided with a tap coefficient controller
6
which automatically correct the coefficient of the equalizer
2
by the use of the information before and after the equalization.
However, the numbers of taps should be increased to enhance the equalizing performance in the second structure. This increases the output delay.
Moreover, the pipeline of the circuit is required for the multipliers (not shown) in the equalizer
2
in order to perform the operation at a high speed. This also increases the output delay. As a result, the delay due to the equalizer
2
often exceeds ten stages.
In the meantime, the system adaptively follows for the inputted signal in the second structure. Therefore, the second structure is resistant to the deterioration with time and any operating environment.
However, the loop delay of PLL is
Dickstein , Shapiro, Morin & Oshinsky, LLP
Tran Thang V.
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