Miscellaneous active electrical nonlinear devices – circuits – and – Specific signal discriminating without subsequent control – By amplitude
Reexamination Certificate
1998-05-20
2001-03-06
Callahan, Timothy P. (Department: 2816)
Miscellaneous active electrical nonlinear devices, circuits, and
Specific signal discriminating without subsequent control
By amplitude
C341S122000, C341S126000
Reexamination Certificate
active
06198313
ABSTRACT:
FIELD OF THE INVENTION
This invention relates to sample-and-hold circuits for use in electronic systems. More particularly, it relates to so-called infinite sample-and-hold circuits and their uses. These uses include, among others, demultiplexing an analog input signal (e.g., a voltage or voltages from a DAC) to multiple outputs at which the signal value may be held for an indefinite (colloquially, “infinite”) duration. Such application is particularly useful in test systems, to set multiple voltages from a single DAC.
BACKGROUND OF INVENTION
Sample-and-hold circuits (also called sample-and-hold amplifiers, and abbreviated in the singular as an “sha”) are widely used in electronic systems, particularly where it is necessary to convert an analog signal into a digital stream or into a digital word for further processing.
In many applications, it is desired that the sample-and-hold circuitry hold on its output for a considerable time the value of the sampled input signal. Frequently, the analog signal (which may be a voltage or a current but is shown in the illustrations herein as a voltage) is sampled onto a capacitor which is used to hold the sampled value or a voltage representing same. A problem exists in the use of such capacitor-based circuits, however, in that the analog voltage level stored on a holding capacitor will “droop”—i.e., steadily fall—over the hold interval, principally as a result of current leakage. Attempts have been made to minimize the impact of this droop by improving the quality of hold capacitors and by ensuring that the holding capacitors are connected to buffers specially designed to draw negligible input current. Also, the capacitance may be increased to reduce droop, but this has a negative impact on the circuit's ability to process high speed signals.
In capacitor-based sample-and-hold circuits, therefore, if the sampled value must be stored for any significant amount of time, the capacitor must be periodically recharged by highly accurate sub-circuits, to refresh the held voltage. This imposes an undesirable overhead on the circuitry and is particularly problematic in situations where a number of sample-and-hold circuits are used, requiring regular polling to refresh stored charges and possibly slowing down the overall operation.
Of particular note, it is sometimes desirable to be able to hold a series of analog sample values of an input signal, and that the held values be—and remain during a long hold period—highly accurate representations of the input at the time of sampling. Using capacitor-based circuitry requires at least one holding capacitor for each sample, in addition to the requisite refresh circuitry. Holding capacitors, however, typically are physically large elements and occupy a considerable amount of area on a die if they are fabricated monolithically with the circuitry. This limits the area available for other components and circuits and raises the cost of the product in which the sample-and-hold circuits are used. If capacitors external to the die are employed, they add substantial cost and physical size as well as introducing unwanted temperature dependencies.
To this end, there have been developed certain so-called “infinite” sample-and-hold circuits (“ISHA”) wherein a digital-to-analog converter generates analog voltage which is compared with an input analog signal and a control circuit forces the generated analog voltage to equal the input analog voltage. The generated analog voltage may then be maintained by maintaining the digital code input to the DAC. However, the DAC may introduce linearity errors, making it difficult to reproduce accurately the input analog signal.
As shown in National Semiconductor's application note publication AN-294, one approach to providing an infinite sample-and-hold amplifier uses a separate ADC and DAC in combination with external circuitry. The disclosed approach, however, requires a large number of discrete components. Further, the accuracy of the system is limited by the accuracy of the two converters; to achieve greater than eight-bit accuracy requires expensive components. Additionally, offset errors in the converters and output buffer, together with gain errors, all combine to reduce the ability to accurately reproduce the input voltage at the output.
Even when the components for such an ISHA are integrated into a single chip, the overall accuracy is still limited by the converters and by the matching between the ADC and DAC.
A variation on this approach is shown in National Semiconductor's application note AN-245. There, the architecture employs a DAC, a successive approximation register (SAR) and a comparator to converge the output voltage to the input sample. However, this approach requires multiple external components and suffers due to offset errors, sample and hold droop, and other factors.
Additionally, in certain types of equipment, such as automated test equipment (ATE), it is desirable to employ digital to analog converters (DACs) to generate from digital control signals analog test signals for driving devices to be tested. In such situations, either a DAC is provided for each signal level required or, if a good sample-and-hold circuit is available, a single DAC output is demultiplexed using a (capacitor-based) sample-and-hold circuit for each level needed. The DAC approach requires accurate high resolution DACs, which are expensive, and using capacitor-based sample-and-hold circuits requires extensive refresh circuitry.
SUMMARY OR THE INVENTION
Accordingly, there is shown herein an infinite sample-and-hold circuit which does not suffer from the aforementioned disadvantages. Such a sample-and-hold circuit will hold a sampled analog voltage (or, equivalently, a voltage representing a sample analog current) indefinitely without the need for refresh circuitry, and does not rely on external components such as capacitors or on highly accurate compensation sub-circuits.
One aspect of the invention is an infinite sample-and-hold circuit which employs a DAC and an ADC coupled with a mode control circuit. In acquisition mode, the mode control circuit connects the analog input signal to the ADC. The ADC drives the DAC and when the DAC output equals the analog input, the mode control circuit disconnects the analog input and the DAC drives the output in hold mode. The mode control circuit preferably includes a comparator/buffer circuit including switching circuitry.
Another aspect of the invention is an infinite sample-and-hold circuit comprising a DAC with good differential non-linearity (DNL) performance, in conjunction with a SAR, to converge an output to an analog input value. Both the digital input to the DAC and the analog DAC output may be available externally. (Having the digital input of the DAC available externally allows the DAC output to be driven to a predetermined value established by a digital input word. For example, this may be a test signal value or a value it is desired to reproduce from a corresponding, previously supplied analog input signal.) The DAC has a buffer stage (or, more properly, a comparator/buffer stage) which is used in two modes: (1) open loop, as a comparator, and (2) closed loop, as a buffer. During acquisition, the comparator mode is used, while in hold mode the buffer mode is used. The utilization of the same amplifier to provide both functions allows cancellation of offset errors otherwise introduced by the comparator and buffer, at least to a first order.
According to another aspect of the invention, an ISHA includes a switching mechanism which allows the analog input to be switched to the ISHA output during sampling (i.e., acquisition). This allows the output to be controlled during acquisition and allows the output circuitry to slew and settle during the acquisition process.
According to a further aspect, the invention includes, in combination with one of the previous aspects, an output buffer and a switching mechanism which prevent the input being loaded by the output load during acquisition.
Yet another aspect of the invention is a
Geraghty Donal
Kenny Christopher A.
Kirby Patrick
Poucher Patrick F. M.
Callahan Timothy P.
Nguyen Hai L.
Wolf Greenfield & Sacks P.C.
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