Pulse or digital communications – Equalizers – Automatic
Reexamination Certificate
2007-10-30
2007-10-30
Payne, David C. (Department: 2611)
Pulse or digital communications
Equalizers
Automatic
C340S870030, C380S265000, C455S307000, C708S420000
Reexamination Certificate
active
10615004
ABSTRACT:
A multiplierless IIR filter incorporates power-of-two coefficients to perform shift operations to reduce space and increase speed. To optimize performance, a genetic algorithm generates the power-of-two coefficients. The filter architecture includes shift registers to receive input samples and previous outputs. A shifter stage is employed to perform shift operations for the input samples and previous outputs based on corresponding power-of-two coefficients. Products are added by parallelism and sequential pipelining to produce an output.
REFERENCES:
patent: 4862402 (1989-08-01), Shah et al.
patent: 2002/0126858 (2002-09-01), Yeum
patent: 2002/0131487 (2002-09-01), Butler et al.
patent: 2003/0083852 (2003-05-01), Muhammad et al.
Yu et al., “New Natural Selection Process and Chromosome Encoding for the Design of Multiplierless Lattice QMF Using Genetic Algorithm,” 2001 IEEE, pp. 1273-1276.
Sriranganathan et al., “Design of 2-D Multiplierless FIR Filters Using Genetic Algorithms,” Genetic Algorithms in Engineering System: Innovations and Applications Sep. 12-14, 1995, Conference Publication No. 414, © IEE, 1995, pp. 282-286.
Bhattacharya et al., “Multiplierless Implementation of Recursive Digital Filters Using a Class of Low Sensitivity Structures,” International Symposium on Signal Processing and its Applications (ISSPA), Kuala Lumpur, Malaysia, Aug. 13-16, 2001, Organized by the Dept. of Microelectronics and Computer Engineering, UTM, Malaysia and Signal Processing Research Centre, QUT, Australia, 2001 IEEE, pp. 611-614.
Lee et al., “GA-based design of multiplierless 2-D state-space digital filters with low roundoff noise,” IEE Proc.-Circuits Devices Syst., vol. 145, No. 2, Apr. 1998, pp. 118-124.
Lee et al., “GA-Based Design of Multiplierless 2-D Digital Filters with Very Low Roundoff Noise,” Proceedings of IEEE Asia Pacific Conference on Circuits and Systems '96, Nov. 18-21, 1996, Seoul, Korea, 1996, IEEE, pp. 223-226.
Bhattacharya et al., “Multiplierless Implementation of Bandpass and Bandstop IIR Digital Filters,” Institute of Signal Processing, Tampere University of Technology, P. O. Box 553, Tampere, FIN 33101, Finland, 2002 IEEE, pp. III-3184-III-3187.
Bhattacharya et al., “Multiplierless Implementation of Recursive Digital Filters Based on Coefficient Translation Methods in Low Sensitivity Structures,” Tampere International Center for Signal Processing, Tampere University of Technology, P. O. Box 553, Tampere, FIN 33101, Finland, 2001 IEEE, pp. II-697-II-700.
Cemes et al., “Genetic approach to design of multiplierless FIR filters,” Electronics Letters, 25thNov. 1993, vol. 29, No. 24, pp. 2090-2091.
Mao et al., “Design and Multiplierless Implementation of Two-Channel Biorthogonal IIR Filter Banks with Low System Delay,” Dept. of Electrical and Computer Engineering, University of Victoria, Victoria, B.C., Canada V8W 3P6, Dept. of Electrical and Electronic Engineering, University of Hong Kong, Pokfulam Road, Hong Kong, 2001 IEEE, pp. II-465-II-468.
Hounsell et al., “Evolutionary Design and Adaptation of Digital Filters Within an Embedded Fault Tolerant Hardware Platform,” Department of Electronics and Electrical Engineering, The University of Edinburgh, King's Buildings, Mayfield Rd, Edinburgh EH9 3JL, 2001 IEEE, pp. 127-135.
Oh et al., “Design of Discrete Coefficient FIR and IIR Digital Filters with Prefilter-Equalizer Structure Using Linear Programming,” IEEE Transactions on Circuits and Systems—II: Analog and Digital Signal Processing, vol. 47, No. 6, Jun. 2000, pp. 562-565.
Wiatr et al., “Implementation of real time image convolutions in FPGA structures,” pp. 1-10.
Wiatr et al., “Constant Coefficient Multiplication in FPGA Structures,” AGH Technical University, Institute of Electronics, Mickiewicza 30, 30-059 Kraków, Poland, pp. 1-8.
Venkatachalam et al., “Adaptive Linear Prediction with Power-of-Two Coefficients,” Electrical & Computer Engineering, Utah State University, Logan, UT 84322-4120, Electrical & Computer Engineering, University of Colorado, Boulder, CO 80309-0425, 2001, IEEE, pp. 533-537.
Thamvichai et al., “Design of 2-D Multiplierless Filters Using the Genetic Algorithm,” Electrical & Computer Engineering, University of Colorado, Boulder, CO 80309, Electrical & Computer Engineering, Utah State University, Logan, UT 84322-4120, 2001 IEEE, pp. 588-591.
Jamro et al., “FPGA Implementation of Addition as a Part of the Convolution,” AGH Technical University, Institute of Electronics, Mickiewicza 30, 30-059 Kraków, Poland, pp. 1-9.
Jamro et al., “Convolution Operation Implemented in FPGA Structures for Real-Time Image Processing,” AGH Technical University, Institute of Electronics, pp. 1-6.
Ghanekar et al., “Implementation of Recursive Filters Using Highly Quantized Periodically Time-Varying Coefficients,” Department of Electrical and Computer Engineering, University of Massachusetts, Amherst, MA 01003, 1991 IEEE, pp. 1625-1628.
Hartnett et al., “IIR Filters with Reduced Multipliers Using Cyclotomic Polynomial Numerators,” U. S. Coast Guard Academy, New London, CT 06320, University of Rhode Island, Kingston, RI 02881, 1992 IEEE, pp. IV-321-324.
Milić “Design of Multiplierless Elliptic IIR Filters,” Mihajlo Pupin Institute, Volgina 15, 11000 Belgrade, Yugoslavia, IRITEL Institute, Batajnicki put 23, 11080 Belgrade, Yugoslavia, 1997 IEEE, p. 2201-2204.
Lian, “FPGA Implementation of High Speed Multiplierless Frequency Response Masking FIR Filters,” Electrical Engineering Department, National University of Singapore, 10 Kent Ridge Crescent, Singapore 119260, 2000 IEEE, pp. 317-325.
Lutovac et al., “Approximate Linear Phase Multiplierless IIR Halfband Filter,” IEEE Transactions on Signal Processing Letters, vol. 7, No. 3, Mar. 2000, pp. 52-53.
Chan et al., “Multiplierless Perfect Reconstruction Modulated Filter Banks with Sum-of-Powers-of-Two Coefficients,” IEEE Signal Processing Letters, vol. 8, No. 6, Jun. 2001, pp. 163-166.
Milić et al., “Design of Multiplierless Elliptic IIR Filters with a Small Quantization Error,” IEEE Transactions on Signal Processing, vol. 47, No. 2, Feb. 1999, p. 469-479.
Thamvichai et al., “Design of 2-D Multiplierless IIR Filters Using the Genetic Algorithm,” IEEE Transactions on Circuits and Systems—I: Fundamental Theory and Applications, vol. 49, No. 6, Jun. 2002, pp. 878-882.
Bose Tamal
Sharma Chirag RamGopal
Shaw Alan W.
Thamvichai Ratchaneekorn
DSouza Adolf
Payne David C.
Stoel Rives LLP
Thompson John R.
Utah State University
LandOfFree
Infinite impulse response multiplierless digital filter... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Infinite impulse response multiplierless digital filter..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Infinite impulse response multiplierless digital filter... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3833538