Semiconductor device manufacturing: process – Chemical etching – Combined with the removal of material by nonchemical means
Reexamination Certificate
2000-11-17
2003-05-20
Zarabian, Amir (Department: 2822)
Semiconductor device manufacturing: process
Chemical etching
Combined with the removal of material by nonchemical means
C438S459000, C438S464000, C216S091000
Reexamination Certificate
active
06566267
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to an inexpensive process for producing a multiplicity of semiconductor wafers with a local flatness, expressed as the SFQR
max
value for a surface grid of 25 mm×25 mm, of less than or equal to 0.13 &mgr;m. Semiconductor wafers with a high flatness of this nature are suitable for use in the semiconductor industry, in particular for the fabrication of electronic components with line widths of less than or equal to 0.13 &mgr;m.
2. The Prior Art
A semiconductor wafer which is to be suitable in particular for the fabrication of electronic components with line widths of less than or equal to 0.13 &mgr;m must have a high local flatness in all partial areas. A suitable measure of flatness which takes into account the focussing capabilities of a stepper, is the SFQR (site front-surface referenced least squares−range=range of the positive and negative deviation from a front surface defined by minimizing the mean square error for a component area of defined size). The parameter SFQR
max
specifies the maximum SFQR value for all the component areas on a semiconductor wafer. A generally accepted rule of thumb states that the SFQR
max
value of a semiconductor wafer must be less than or equal to the possible line width on this wafer for semiconductor components that are to be produced on it. If this value is exceeded, the stepper experiences focussing problems and the component in question is thus lost.
The final flatness of a semiconductor wafer is generally produced by a polishing process. In order to improve the flatness values of a semiconductor wafer, apparatuses and processes for the simultaneous polishing of front and back sides of the semiconductor wafer have been provided and developed further. This so-called double-side polishing is described for example in U.S. Pat. No. 3,691,694. In accordance with an embodiment of double-side polishing which is described in EP 208 315 B1, semiconductor wafers in carriers which are made of metal or a plastics material and have suitably dimensioned cutouts are moved along a path. This path is predetermined by the machine and process parameters between two rotating polishing plates, which are covered with a polishing cloth, in the presence of a polishing fluid, and hence polished.
It is known to integrate double-side polishing into process sequences for producing semiconductor wafers. EP 754 785 A1 describes the sequence of sawing a semiconductor crystal, followed by edge rounding, double-side polishing and final polishing of the semiconductor wafers obtained. In EP 755 751 A1, it is proposed to employ a double-side grinding process between the edge rounding and double-side polishing. EP 798 405 A2 describes the sequence of sawing—edge rounding—grinding—alkaline etching—double-side polishing. The preferred embodiments of U.S. Pat. No. 5,756,399 include the process sequence of sawing—grinding—alkaline etching—edge rounding—double-side polishing. U.S. Pat. No. 5,899,743 describes the sequence of steps of sawing—edge rounding—lapping—double-side polishing—edge polishing—final polishing. DE 198 33 257 C1 discloses the process sequence of sawing—edge rounding—grinding —etching—double-side polishing—final polishing, the etching in this case being carried out using an improved acid etching process. A common feature of these process sequences is that after the double-side polishing they lead to a semiconductor wafer with SFQR
max
values of greater than 0.13 &mgr;m.
The production of a semiconductor wafer with SFQR
max
values of less than or equal to 0.13 um is described in EP 961 314 A1 which describes the use of expensive plasma etching processes. This production also forms the subject of DE 199 05 737 A1. This discloses an improved double-side polishing process by maintaining tightly restricted thickness ratios between carrier thickness and thickness of the semiconductor wafer after the polishing process. This application specifies that preferably from 10 &mgr;m to 60 &mgr;m, and particularly preferably 20 &mgr;m to 50 &mgr;m, of material are removed in the case of the polishing of silicon wafers. A common feature of both processes is that a percentage of wafers produced in this way do not satisfy the quality features stipulated for further processing, such as a surface which is free from flaws in terms of scratches, stains and light point defects. This percentage always occurs in practical operation, and thus has to be discarded, which has an adverse effect on the production costs for wafers of this nature.
SUMMARY OF THE INVENTION
Therefore, it is an object of the present invention to provide a process for producing a multiplicity of semiconductor wafers with an SFQR
max
value of less than or equal to 0.13 &mgr;m which is superior to the known processes of the prior art in terms of the production costs. Furthermore, it was intended that the further properties of the semiconductor wafers produced using this process should be at least as good as those of semiconductor wafers produced according to the prior art.
This object is achieved according to the present invention by providing a process for producing a multiplicity of semiconductor wafers, which comprises the following individual steps:
(a) simultaneously polishing a front side and a back side of each semiconductor wafer between rotating polishing plates with a polishing fluid being supplied, the semiconductor wafer in each case resting in a cutout in a carrier and being kept on a specific geometric path, and all semiconductor wafers having a thickness t
1
following the polishing;
(b) assessment of each semiconductor wafer with regard to quality features which are stipulated for further processing;
(c) further simultaneously polishing a front side and a back side of each of those semiconductor wafers which, according to quality inspection (b), do not satisfy the stipulated quality features, these semiconductor wafers having a thickness t
2
following the further polishing; and
(d) further assessment of each of those semiconductor wafers which were fed to step (c) with regard to quality features stipulated for further processing.
An essential feature of the invention is that those semiconductor wafers from a multiplicity of double-side polished semiconductor wafers which do not satisfy the quality features specified for further processing can be fed to a further double-side polishing step. Thus there will be an increasing of the overall yield and therefore a reduction in production costs. Also the reduction in thickness can be selected to be sufficiently small for it to be possible to maintain the standard tolerances for the wafer thickness which are required in semiconductor fabrication. In the description which follows, double-side polishing in which only a relatively small reduction in thickness is desired is referred to as flash DSP. The fact that a flash DSP process of this nature allows flawed semiconductor wafers to be machined with a high yield without having an adverse effect on the local geometry values was unexpectedly surprising and not predictable.
The starting product for the process is a multiplicity of semiconductor wafers which have been cut from a crystal in a known way. For example these wafers are from a single silicon crystal which has been cut to length and cylindrically ground, have had their edges rounded by means of a suitably profiled grinding wheel or a plurality of different grinding wheels of this nature and whose front and/or back sides have if appropriate been treated by means of grinding, lapping and/or etching processes. If desired, the crystal may be provided with one or more orientation features in order to identify the crystal axes, for example with a notch and/or a flat. Furthermore, it is possible for the edge of the semiconductor wafers to be polished before the process according to the invention is carried out.
The end product of the process is a multiplicity of double-side polished semiconductor wafers which satisfy the demands imposed on semiconducto
Perkins Pamela
Wacker Siltronic Gesellschaft für Halbleitermaterialien AG
Zarabian Amir
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