Semiconductor device manufacturing: process – Forming bipolar transistor by formation or alteration of... – On insulating substrate or layer
Reexamination Certificate
1999-07-26
2002-02-26
Elms, Richard (Department: 2824)
Semiconductor device manufacturing: process
Forming bipolar transistor by formation or alteration of...
On insulating substrate or layer
C438S410000, C438S424000, C438S427000
Reexamination Certificate
active
06350657
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to semiconductor wafers, and more particularly to a method of manufacturing a silicon on insulator (SOI) wafer from a monocrystalline silicon substrate.
BACKGROUND OF THE INVENTION
As is known in the microelectronics industry, monocrystalline silicon wafers are the most widely used substrate for the manufacture of electronic devices. As an alternative to silicon wafers, composite SOI wafers have been proposed which are formed of two silicon layers, one thinner than the other and separated by a silicon dioxide layer.
A method of manufacturing SOI wafers is the subject of European patent application No. 98830007.5 filed on Jan. 13, 1998 to the assignee of the present invention. A similar method is described below with reference to
FIGS. 1
to
8
.
First, a first silicon dioxide layer between 20 and 60 nm thick is grown on a major surface
3
of a substrate formed of a monocrystalline silicon wafer
2
. Then a first layer of silicon nitride between 90 and 150 nm thick and a second silicon dioxide layer between 100 and 600 nm thick produced by decomposition of tetraethyl orthosilicate (TEOS), are deposited thereon. A resist layer and a masking operation are used to define in plan view, for example, a grid of rectangular areas. Dry etching of the uncovered portions of the TEOS oxide layer, of the first nitride layer, and of the first oxide layer is then carried out and the residual resist is then removed producing the structure shown in cross-section in FIG.
1
. The portions of the first oxide layer, of the first nitride layer, and of the TEOS oxide layer remaining after the dry etching are indicated as
4
,
5
and
6
, respectively. Together these define protective plaques
7
covering portions
8
′ of the monocrystalline silicon substrate
2
.
The protective plaques
7
form a mask, generally indicated
9
, for subsequent selective anisotropic etching of the silicon substrate
2
. This treatment etches the portions of the substrate
2
indicated
8
″, which are not protected by the mask
9
, so that initial trenches
10
are formed (FIG.
2
).
As shown in
FIG. 3
, the structure is then subjected to an oxidation step which leads to the formation of a third silicon dioxide layer
11
, between 20 and 60 nm thick, which covers the walls and the bases of the initial trenches
10
. A second silicon nitride layer
12
between 90 and 150 nm thick is then deposited.
The method continues with dry anisotropic etching without masking, during which the horizontal portions of the second silicon nitride layer
12
are removed. During the dry etching, the first nitride layer
5
is protected by the TEOS oxide layer
6
. The third oxide layer
11
which is disposed in the bases of the initial trenches
10
is removed by a wet process. This produces the structure shown in
FIG. 4
, in which it is possible to see the portions
8
′, still covered on the top by the mask
9
and on the sides (on the vertical walls of the initial trenches
10
) by portions
11
′ and
12
′ of oxide and nitride, respectively, and the uncovered bases
15
of the initial trenches
10
.
Anisotropic etching of the silicon is then carried out with the use, of the mask
9
modified by the addition of the oxide and nitride portions
11
′ and
12
′, respectively. The uncovered silicon in the bases
15
of the initial trenches
10
is etched for a predetermined period to give final trenches
16
having a desired depth. It will be noted that the difference between the depth of the final trenches
16
and that of the initial trenches
10
determines the dimensions of the buried oxide layer, and, hence, the electrical characteristics of the SOI wafer, as will be explained further below. The etching depths are therefore selected on the basis of the specifications of the SOI wafer to be produced.
The monocrystalline silicon substrate thus treated is now formed by a base portion, indicated
2
′, and by a plurality of pillars
18
extending from the base portion
2
′. The structure shown in
FIG. 5
is thus produced, in which the nitride portions
5
and
12
′ are no longer separate and are generally indicated
19
, and the oxide portions
4
and
11
′ are generally indicated
20
. The portions
19
and
20
with the overhanging TEOS oxide portions
6
together form a mask
30
.
The silicon substrate is then subjected to selective oxidation with the use of the mask
30
to protect the silicon on the tops of the pillars
18
from oxidation. The process continues until the portions of the pillars
18
which are not protected by the mask
30
are completely converted into silicon dioxide. In practice, a gradual growth of the oxide regions takes place at the expense of the silicon regions, starting from the side walls of the final trenches
16
, towards the interior of the pillars and partially also into the base portion
2
′. Since the volume of silicon dioxide which is formed is greater than that of the initial silicon, the oxide regions being formed gradually occupy the space in the final trenches
16
until they close them completely and are joined together. The oxidation step terminates automatically when the pillars
18
are completely oxidized (naturally apart from their tops or tips
21
, which are protected by the mask
30
). A continuous oxide region
22
is thus formed, most of which is buried, as shown in
FIG. 6
, in which vertical lines indicate the surfaces on which the oxide regions join.
The TEOS oxide portions
6
and the nitride portions
19
and oxide portions
20
which form the mask
30
are then eliminated by selective etching so as to uncover the tips
21
which are intended to form the seeds for subsequent epitaxial growth. The resulting structure is shown in perspective in FIG.
7
. The epitaxial growth step is performed in a manner such as to prevent nucleation of polycrystalline silicon in the uncovered areas of the buried oxide region
22
. Moreover, a high lateral/vertical growth ratio is selected so as to achieve, first of all, growth of the silicon sideways around the tips
21
until the trench portions which are still open are filled, and then growth of an epitaxial layer
23
in a direction perpendicular to the major surface of the substrate. After an optional chemical-mechanical lapping or polishing step to level the surface of the layer
23
, the final structure of the SOI wafer shown in
FIG. 8
is obtained.
An SOI wafer is thus formed from a normal monocrystalline silicon substrate with the use of process steps which are common in microelectronics, with much lower costs than those of the methods currently used for the production of SOI wafers. However, the implementation of the method described above imposes constraints. To produce a continuous buried oxide layer it is necessary for the areas between adjacent trenches, which define the widths of the pillars, to be as narrow as possible. On the other hand, the minimum width of the pillars is fixed by the minimum thickness required for the residual monocrystalline silicon on the buried oxide layer (that is the tips
21
on the layer
22
, with reference to FIG.
7
), to ensure an adequate crystallographic quality of the epitaxial layer subsequently grown. Moreover, the widths of the pillars cannot be as large as may be desired but must be selected so as to ensure that the silicon disposed between adjacent trenches is completely converted into oxide. It is also necessary for the trenches to be as narrow as possible consistent with the thicknesses required by the method for the nitride and oxide layers deposited or grown. Finally, the known method described above is greatly limited by the dimensional ratios between the trenches and the pillars.
SUMMARY OF THE INVENTION
An object of the present invention is to provide a method of manufacturing an SOI wafer which is not limited by the dimensional ratios between the trenches and the pillars.
This and other objects can be achieved by the method according to the invention including th
Barlocchi Gabriele
Mastromatteo Ubaldo
Villa Flavio
Allen Dyer Doppelt Milbrath & Gilchrist, P.A.
Elms Richard
Jorgenson Lisa K.
STMicroelectronics S.r.l.
Wilson Christian D.
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