Industrial robot control apparatus

Electricity: motive power systems – Positional servo systems – Program- or pattern-controlled systems

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Details

3185881, 318567, 364513, 364191, 364200, 901 3, G05B 1942

Patent

active

049655000

DESCRIPTION:

BRIEF SUMMARY
DESCRIPTION

1. Technical Field
The present invention relates to a control apparatus for an industrial robot, and more particularly, to a technique of loading a plurality of tasks into a plurality of arithmetic and control units in an initialization period when control of the industrial robot is shared by the arithmetic and control units.
2. Background Art
The control of an industrial robot has become more sophisticated and complex, and a demand has arisen for a high-performance control apparatus. But, instead of using such a high-performance control apparatus, a technique of using a plurality of arithmetic and control units, e.g., microcomputers, and sharing the control of an industrial robot, is occasionally adopted. Namely, by using a plurality of microcomputers each having a relatively low performance and distributing the overall tasks, the overall processing ability is improved to an extent such that complex control of the industrial robot can be satisfactorily performed. The number of microcomputers to be used is determined by the amount of control needed for the industrial robot, the processing ability of each microcomputer, the cost of the control apparatus, and the like.
Each microcomputer comprises a CPU, a RAM, and a ROM, and one of the microcomputers further comprises an I/O unit to enable an interface with a mechanical section, a drive section, a sensor section, and the like, of the industrial robot. These microcomputers can be interlinked through a bus.
An external storage unit, e.g., a magnetic disk unit, is connected to the microcomputers through the bus, and stores the various tasks to be executed in each microcomputer and an operating system (OS) for executing these tasks. In an initialization period immediately after a power source is turned ON, and OS is loaded in each RAM by an initial loader, e.g., a bootstrap loader, in each microcomputer, and then tasks are loaded in each RAM in accordance with a predetermined task assignment. As described above, the OS and the tasks are previously stored in the magnetic disk unit, and the OS and a corresponding task are loaded in the RAM of each microcomputer during the initialization period, for the following reasons. Assuming that the OS and the corresponding task are fixed in each microcomputer, then they must be stored in, e.g., a ROM, to be retained after the power source is turned OFF. But, to allow this storing in the ROM, first the ROM must have a large capacity, thereby posing a problem in terms of cost, and second, although the contents of a task are often changed, such changes cannot be effectively processed. Therefore, the ROMs can be replaced by a simple non-volatile memory such as a floppy disk, in which an OS and a task of a given microcomputer are store, connected to each microcomputer, and the stored OS and task loaded from the floppy disk into each RAM during the initialization period. In this method, however, floppy disks are required for a plurality of microprocessors, and thus the overall cost is inevitably increased. Accordingly, a magnetic disk unit is commonly connected to all of the microcomputers, and the initial loading of each RAM is performed during the initialization period as described above.
A common memory, e.g., a shared memory, is also connected to the bus. In the above system wherein a plurality of microcomputers are connected on the same level without a supervisory computer, to thereby constitute a non-hierarchical structure, when the processing of tasks in the microcomputers is to be synchronized, this synchronization is established by, e.g., a mailbox scheme or a semaphore technique, by using this shared memory.
As described above, in the conventional system, the assignment of programs (tasks) to be executed by the respective microcomputers is determined when the programs are prepared, but this task assignment is not always easy. An excessive load may be applied to one microprocessor but relatively small loads applied to the other microprocessors, and in this case, the microprocessor to which the excessive loa

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