Semiconductor device manufacturing: process – Making passive device
Reexamination Certificate
1999-11-01
2002-05-28
Nelms, David (Department: 2818)
Semiconductor device manufacturing: process
Making passive device
C438S383000
Reexamination Certificate
active
06395611
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates generally to integrated circuits and, more particularly, to an inductor and a method of manufacturing an inductor in an integrated circuit.
BACKGROUND OF THE INVENTION
The integration of high-Q inductors with high-density CMOS technologies faces limitations because of conflicts in substrate requirements. Some CMOS technologies use standard substrates that include a P− doped epitaxial layer formed on a P+ bulk substrate. The P+ bulk substrate has a resistivity as low as 1×10
19
cm
−3
. Inductors fabricated using conventional back-end processes are severely degraded because of eddy current losses in the standard substrate.
For example, inductors formed on standard substrates have been reported having a maximum quality factor Q of approximately three (3). Quality factor Q is a measure of inductor performance. A higher Q signifies a better inductor while a lower Q signifies a worse inductor. Although the P+ epitaxial layer degrades inductor performance, it suppresses latchup and provides impurity gettering in CMOS devices. Therefore, changing to a non-degenerate substrate to increase Q translates into a reduction in device density and possible yield loss. Further, a change to a higher resistivity substrate would cause shifts in device characteristics and result in new design rules to satisfy the new latchup conditions. This would require redesign of existing circuit libraries.
SUMMARY OF THE INVENTION
The present invention provides an integrated circuit with a buried layer for increasing the Q of an inductor formed in the integrated circuit. In one illustrative embodiment, an inductor is formed in an integrated circuit having a substrate that includes a P+ buried layer formed between a P− epitaxial layer and a p bulk substrate. In other words, the substrate includes a highly doped buried layer formed between less doped layers. This provides a high Q inductor while preserving device and latchup characteristics. The present invention further relates to providing an increased thickness metal layer to form the body of the inductor to further increase Q.
The present further relates to a low loss interconnect (transmission line). The interconnect is formed in the same manner as the inductor except that the metal layer is not formed in a spiral shape to form an inductor.
It is to be understood that both the foregoing general description and the following detailed description are exemplary, but are not restrictive, of the invention.
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patent: 4458158 (1984-07-01), Maryrand
patent: 4789645 (1988-12-01), Calviello et al.
patent: 5091330 (1992-02-01), Cambon et al.
patent: 5712189 (1998-01-01), Plumton et al.
patent: 5861336 (1999-01-01), Reedy et al.
patent: 6153473 (2000-11-01), Calafut et al.
Belk Nathan
Cochran William Thomas
Frei Michel Ranjit
Goldthorp David Clayton
Moinian Shahriar
Agere Systems Guardian Corp.
Grillo Anthony
Le Thao
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