Inductor-less RF/IF CMOS buffer for 50&OHgr; off-chip load...

Details Inductor-less RF/IF CMOS buffer for 50&OHgr; off-chip load... Inductor-less RF/IF CMOS buffer for 50&OHgr; off-chip load...

2001-11-28

2002-08-20

Ton, My-Trang Nu (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Current driver

C327S054000, C330S260000

Reexamination Certificate

active

06437612

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The invention relates to CMOS integrated semiconductor circuits, and more particularly to a 50&OHgr; analog buffer amplifier operating in the RF/IF frequency range which avoids using external inductors.
2. Description of the Related Art
Despite the many buffer amplifier designs of the related art, CMOS equivalents of bipolar buffer amplifiers, like the Darlington or the class AB circuit, tend to be inferior. We will demonstrate this point by examining a CMOS equivalent of the “Darlington pair” buffer amplifier in
FIG. 1
, and a CMOS equivalent class AB buffer amplifier in FIG.
2
.
FIG. 1
shows an NMOS transistor M
1
coupled in series with a current source I
1
coupled between a positive voltage supply V
DD
and ground (GND). The gate of M
1
is coupled via capacitor C
1
to input v
i
and via resistor R
1
to another voltage supply V
R
. Similarly coupled between V
DD
and ground is a second NMOS transistor M
2
in series with a second current source I
2
. The gate of M
2
is coupled to the source of M
1
, and the source of M
2
is coupled via a second capacitor C
2
to output V
o
. C
p
is the total parasitic capacitance of the pad, pin and printed circuit board (PCB) and R
L
is the external load, typically 50 ohm.
However, the CMOS version does not work as well as the bipolar one. The expression for voltage gain of the circuit in
FIG. 1
, where g
m2
is the transconductance of M
2
, is given by
Av
=
v
o
v
i
≅
g
m2
⁢
R
L
1
+
g
m2
⁢
R
L
(
1
)
From (1) we can easily see that to achieve Av=1, it is necessary to have g
m2
R
L
>>1. This is a very difficult requirement—even in sub-micron CMOS—since g
m2
must be very high as R
L
is equal to 50&OHgr; only. Very large sizes for M
2
and very large values for I
2
are required to achieve this. Such transconductances, however, are much more easily achievable with bipolar devices. In CMOS technology this circuit usually has a voltage gain that is substantially less than unity while driving 50&OHgr;.
FIG. 2
shows a four transistor CMOS equivalent of a bipolar class AB push-pull buffer amplifier. The section from input v
i
to M
1
, I
1
is identical to that of FIG.
1
. However, M
2
is a PMOS transistor which has its source coupled via I
2
to +V
DD
. The drain of M
2
is connected to ground and its gate it coupled to the gate of M
1
. M
1
and M
2
drive a CMOS output stage comprising NMOS transistor M
3
and PMOS transistor M
4
coupled between +V
DD
and ground. The gate of M
3
connects to the source of M
2
and the gate of M
4
connects to the source of M
1
. The junction of M
3
and M
4
couples via C
2
to output v
o
. Coupled between the output and ground are C
p
and the load R
L
as described in
FIG. 1
above.
In these and subsequent figures, like parts are identified by like numerals or characters.
This circuit is superior to that in
FIG. 1
in some respects. The quiescent current can be low, the sizes of the output transistors M
3
and M
4
can also be smaller. However the disadvantages are as follows. Firstly, the signal swing is limited at the output to V
DD
−(V
GS4
+V
GS3
) compared to V
DD
−V
GS2
in FIG.
1
. Since V
GS
is of the order of 1V, this is a substantial loss with V
DD
=3V which is quite common for deep sub-micron CMOS technology. Secondly, the DC voltage at the sources of M
3
, M
4
, designed to be equal to V
R
=V
DD
/2, may not be realised in practice because of V
GS
mismatches of M
1
, M2, M3 and M
4
. This further degrades the output signal swing of the buffer. Thirdly, neither can this circuit achieve unity voltage gain, when realised with source followers similar to the circuit in FIG.
1
.
A patent search revealed the following U.S. Patents relating to buffer amplifiers: U.S. Pat. No. 6,052,028 (Heaton), U.S. Pat. No. 4,495,471 (Barrett), U.S. Pat. No. 4,471,319 (Metz), and U.S. Pat. No. 4,390,852 (Addis), describe Bipolar and FET buffer amplifiers for different applications. U.S. Pat. No. 5,111,157 (Komiak) describes a buffer with MOS devices but uses a complicated circuit with several inductors. U.S. Pat. No. 5,959,475 (Zomorrodi) and U.S. Pat. No. 5,668,500 (LeFevre) describe CMOS buffers but they are complicated and for a different application. U.S. Pat. No. 5,877,634 (Hunley) discloses a CMOS buffer with a controlled slew rate at the output. The circuit uses a differential circuit for feedback but is otherwise different.
None of the related art satisfies the requirement to provide a 50&OHgr; analog buffer amplifier operating in the RF/IF frequency range (typically 100 MHz-2 GHz) which can be integrated in a CMOS technology because it is difficult to integrate inductors for such frequencies when external inductors are to be avoided. The only off-chip components are the 50&OHgr; load resistor and its coupling capacitor.
SUMMARY OF THE INVENTION
It is an object of at least one embodiment of the present invention to provide a method and circuits for an analog buffer amplifier operating into a 50 ohm load and in the radio frequency/intermediate frequency (RF/IF) range of typically 100 MHz to 2 GHz (MHz=10
6
hertz, GHz=10
9
hertz).
It is another object of the present invention to integrate this analog buffer amplifier in a CMOS technology.
It is yet another object of the present invention to eliminate inductors from the integrated circuit of the analog buffer amplifier.
It is still another object of the present invention to eliminate the need for external inductors.
It is a further object of the present invention is to achieve a voltage gain of one or better.
It is yet a further object of the present invention is to avoid using very large transistors and large current sources.
It is still a further object of the present invention is to provide a large signal swing.
These and many other objects have been achieved by providing buffer amplifier comprising a source-follower plus common drain stage with a feedback path from the output of the common drain stage to the input gate of the source follower stage. The feedback circuit is designed such that the output of the common drain stage can be guaranteed to be at a voltage midway between the positive and the negative voltage supply of the circuit. This is the optimum operating point since it allows the largest signal swing. The transconductance of the feedback amplifier must be small, because the output coupling capacitor cannot be made any smaller to ensure stability of the feedback loop. A small transconductance is realized by biasing the transistors of the feedback amplifier with very low currents; such as by operating them in the weak inversion region. In addition, the transistors of the feedback amplifier can be dimensioned in such a way as to reduce the transconductance even further. Another important fact is that the feedback through the feedback amplifier is only present at DC (direct current) and a very low frequencies. This stabilizes the DC voltage at the drain of the common drain transistor, which, via an output capacitor, is also the output of the buffer amplifier.
These and many other objects and advantages of the present invention will be readily apparent to one skilled in the art to which the invention pertains from a perusal of the claims, the appended drawings, and the following detailed description of the preferred embodiments.


REFERENCES:
patent: 4390852 (1983-06-01), Addis
patent: 4471319 (1984-09-01), Metz
patent: 4495471 (1985-01-01), Barrett
patent: 5047657 (1991-09-01), Seevinck et al.
patent: 5111157 (1992-05-01), Komiak
patent: 5122915 (1992-06-01), Klein et al.
patent: 5668500 (1997-09-01), LeFevre
patent: 5675294 (1997-10-01), Shyu et al.
patent: 5877634 (1999-03-01), Hunley
patent: 5959475 (1999-09-01), Zomorrodi
patent: 6049246 (2000-04-01), Kozisek et al.
patent: 6052028 (2000-04-01), Heaton

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