Inductor for integrated circuits

Details Inductor for integrated circuits Inductor for integrated circuits

2000-11-14

2004-03-30

Donovan, Lincoln (Department: 2832)

Inductor devices

Windings

Having conductor of particular shape

C336S200000, C336S225000, C336S232000, C257S531000, C257S758000

Reexamination Certificate

active

06714113

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to enhancements to inductors for integrated circuit technology and more particularly to structures and methods of making inductors which do not provide a major impact on conventional semiconductor manufacturing techniques.
2. Description of the Prior Art
Producing an on-chip inductor, incorporated with modem integrated circuits is highly desirable for many applications.
One main disadvantage to integrating inductors, particularly over low resistivity substrates, is that significant electric and magnetic field coupling takes place between the inductor element and the conductive substrate. First, this tends to minimize the achieved inductance, since any induced current in the substrate will have a magnetic field oriented in opposition to the magnetic field of the inductor (Lenz's Law). This opposition to the magnetic field of the inductor causes a reduction of the overall magnetic field with increasing frequency, yielding a varying effective inductance. Second, the currents generated in the substrate (either from magnetic or electric fields) lead to power loss (lowered quality factor) and noise coupling.
Prior art, U.S. Pat. No. 5,446,311, by Ewen, Ponnapalli and Soyuer, describes a system for obtaining High Q (quality factor) inductors in silicon technology without expensive metalization. The inductor is formed as a spiral conductor configuration with multiple metal levels in a conventional integrated circuit technology in which inductor turns utilize the multiple metal levels to reduce the inductor resistance. This prior art has limitations in that there would be strong electrical coupling between the inductor and the substrate. Thus a high resistivity substrate (about 10 ohm-cm or higher) would be more suitable for this prior art to produce a reasonable value of Quality Factor (Q) above 5. Also, this system produces a quality factor of only above 5, at radio and microwave frequencies. Using substrates with lower resistivity (example 0.01 ohm-cm) would reduce the quality factor significantly due to eddy currents generated in the substrate.
U.S. Pat. No. 5,083,226, employs dielectric substrate layers, not semiconductor integrated chips, and electronic components are mounted within the inductor volume.
U.S. Pat. No. 5,861,647, inductors are formed using plugs that connect two metal layers. This art requires a special thickness for the interlevel dielectric insulation, which presents a limitation to scaling to smaller devices and extending the operating range of the art.
U.S. Pat. No. 5,917,244, requires special processing with electroless plating method and a nickel containing conductor layer over the substrate layer. U.S. Pat. No. 5,478,773, also requires special processing with plated copper to a thickness of several microns. U.S. Pat. No. 5,793,272, also requires special processing using ferromagnetic cores and a ferromagnetic liner.
U.S. Pat. No. 5,788,854, also has limitations as far as processing is concerned, where an inductor is initially fabricated on a substrate and then integrated with other devices subsequently formed on the substrate. The process steps used to fabricate such other devices utilize temperatures sufficiently low to prevent damaging or destroying the characteristics of the inductor.
In U.S. Pat. No. 5,712,184, special processing is employed where a large number of monocrystalline silicon islands are generated, which silicon islands are insulated from the substrate wafer by means of a dielectric layer, and from each other by means of vertical dielectric material. Also in this prior art, substrates with high resistivity are used, posing another limitation on the invention.
In U.S. Pat. No. 5,656,849, a spiral inductor is presented, but also the inductor in this prior art is not isolated from the substrate.
In U.S. Pat. No. 5,541,135, an inductor requires special processing using electroplating to produce Flip Chip Bumps. U.S. Pat. No. 5,898,991, presents an inductor requiring very special processing producing a structure in which one or more concentric conductive elements are replaced by one or more solid electrically conductive “pins” or “posts” to provide electrical connection between the circuits on each side of a magnetic substrate.
In U.S. Pat. No. 5,801,100, again special processing is required using electroless copper plating to form a nickel containing conductive layer over the substrate layer.
Several references teach alternate forms based on the spiral inductor art, mostly to reduce the series resistance and improve the inductor quality factor. In the article “On-Chip Spiral Inductors with Diffused Shields Using Channel- Stop Implant,” T. Yoshitomi, et al.;
Tech. Dig. Int. Electron Devices Meeting
(
IEDM
), 1998, pp. 540-543, an idea is described which utilizes an extremely shallow diffusion layer in the n-well under the field oxide. The diffused layer is formed by high energy implantation through the field oxide. This art however, required an additional processing mask level, adding to the cost and complexity of the integrated process. This reference also suffers from the problem that the value of the inductance is a function of frequency.
SUMMARY OF INVENTION
To summarize, prior inventions suffer from several problems: Special complicated and expensive processing is required to produce the inductance, high resistivity substrates are required to reduce coupling to the inductor, and the inductance is not constant over a sufficiently wide range of frequencies.
As one would expect, it is desirable that the on-chip integrated inductance be manufactured without adding processing mask levels to the technology. Also it is desirable that the inductors be used for any type of substrate, high or low resistivity, with almost a constant value for a given inductor, in a wide frequency range. The invention described herein solves both problems presented by the prior art.
Thus, it is an object of the instant invention to construct an inductor/transmission line which can be integrated on any VLSI or ULSI circuit technology.
It is another object to provide an inductor which can be used on low or high resistivity substrates, without significant degradation of the quality factor.
The inductor system of this invention utilizes a microstrip transmission line which comprises a center conductor and a fairly wide metal plane below the center conductor. This metal plane is electrically grounded.
These and other objects of the invention will be described in more detail in connection with the accompanying drawings and description of the preferred embodiment of the invention.


REFERENCES:
patent: 5070317 (1991-12-01), Bhagat
patent: 5083236 (1992-01-01), Chason et al.
patent: 5095357 (1992-03-01), Andoh et al.
patent: 5227659 (1993-07-01), Hubbard
patent: 5384274 (1995-01-01), Kanehachi
patent: 5387551 (1995-02-01), Mizoguchi et al.
patent: 5446311 (1995-08-01), Ewen et al.
patent: 5478773 (1995-12-01), Dow et al.
patent: 5541135 (1996-07-01), Pfeifer et al.
patent: 5545916 (1996-08-01), Koullias
patent: 5559360 (1996-09-01), Chiu et al.
patent: 5614743 (1997-03-01), Mochizuki
patent: 5618777 (1997-04-01), Hey-Shipton et al.
patent: 5629553 (1997-05-01), Ikeda et al.
patent: 5656849 (1997-08-01), Burghartz et al.
patent: 5712184 (1998-01-01), Kaiser
patent: 5788854 (1998-08-01), Desaigoudar et al.
patent: 5793272 (1998-08-01), Burghartz et al.
patent: 5801100 (1998-09-01), Lee et al.
patent: 5861647 (1999-01-01), Zhao et al.
patent: 5898991 (1999-05-01), Fogel et al.
patent: 5917244 (1999-06-01), Lee et al.
patent: 6175727 (2001-01-01), Mostov
patent: 6466112 (2002-10-01), Kwon et al.
T. Yoshitomi, et al.; “On Chip Spiral Inductors with Diffused Shields Using Channel-Stop Implant,” Tech Dig. Int. Electron Devices Meeting (IEDM), 1998, pp 540-543.
R.D. Lutz, et al., “Modeling and Analysis of Multilevel Spiral Inductors For RFICS,” Microwave Symposium Digest, 1999 IEEE MTT-S Internation, pp. 43-46, May 1999.
M.S. Sunderarajan, et al., “Simple Accurate Expressions for Planar Spiral Inductan

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