Active solid-state devices (e.g. – transistors – solid-state diode – Heterojunction device – Field effect transistor
Reexamination Certificate
2001-02-02
2003-11-04
Elms, Richard (Department: 2824)
Active solid-state devices (e.g., transistors, solid-state diode
Heterojunction device
Field effect transistor
C257S531000, C257S281000
Reexamination Certificate
active
06642552
ABSTRACT:
BACKGROUND
A book entitled “Nonvolatile Semiconductor Memory Technology”, Edited by William D. Brown and Joe. E. Brewer and published by IEEE Press (1998), ISBN 0-7803-1173-6, states, on page 1 “The ultimate solution—a genuine nonvolatile RAM that retains data without external power, can be read from or programmed like a static or dynamic RAM, and still achieve high-speed, high-density, and low power consumptions at an acceptable cost—remains unfeasible to this day.” On page 6, this book describes a class of nonvolatile memory devices that store a charge on a conducting or semiconducting layer (called “floating gate”) that is completely surrounded by dielectric and an opposing layer (called “control gate”) that together form a capacitor (commonly known as “storage capacitor”).
An article entitled “Applied Materials Introduces New Storage Capacitor Solution for Gigabit DRAMs” dated Jul. 8, 1998 describes use of tantalum pentoxide (Ta2O5) to form storage capacitors in memory devices. Such a storage capacitor cannot hold its charge over an extended period of time and loses a stored data bit unless its charge is refreshed periodically, as described at http://www.ee.cooper.edu/courses/course pages/past courses/EE151/MEMS HO1/. As described therein, the periodic refreshing requires additional memory circuitry and complicates the operation of dynamic random access memory (DRAM) formed from such capacitors.
The above-described periodic refreshing can be avoided by flash memory. There are several kinds of flash memory, including a single-transistor cell and a two-transistor cell as described in an article in Electronic Design, dated Aug. 9, 1999, and entitled “Feature-Rich Flash Memories Deliver High Density” by Dave Bursky. As described therein, a single-transistor cell is employed in a NOR-like logic structure to form a random-access storage array (called “flash EPROM”). Moreover, the two-transistor (or a merged transistor, dual-gate) cell is also a NOR-style configuration (called “flash EEPROM”). On-chip decoding circuits divide an array of two-transistor cells into small blocks (256 bytes to 4 kbytes) that normally enable a smaller portion of the chip to be erased and reprogrammed.
Several issues exist with the flash memory as described in the above-identified book by Brown and Brewer, such as slow trapping, polarization, oxide breakdown/leakage, hot-electron injection, and oxide-hopping conduction, as described in Table 6.2 on page 362
SUMMARY
In accordance with the invention, a semiconductor substrate has formed therein an inductor and a capacitor integrated into a single device (called an “inductive capacitor”). The inductor causes the capacitor to charge faster than the charging of a prior art device that has significant capacitance but negligible inductance (e.g. a device in which the capacitive contribution to the resonant frequency (of an LC circuit formed by such a prior art device) is greater than 90% of the inductive contribution). The device can include any structure that implements the inductive and capacitive functions in an integrated manner. Such a device having a significant inductive effect can be used in any radio-frequency (RF) circuit.
In one embodiment, the device includes a rod-shaped second element (hereinafter simply “plug”) that is located in an interior space defined by a sleeve-shaped first element (hereinafter simply “sleeve”), thereby to form a capacitor (also called “first capacitor”) and an inductor in the same device. The core is separated from the sleeve by a dielectric material (also called “trap material”) that stores an electrical charge when the device is powered off (such as silicon—silicon dioxide interface). An inductive capacitor that includes a trap material between the two elements is also referred to as an “inductive storage capacitor.” Such an inductive storage capacitor is used to implement a nonvolatile memory cell in one application, and a timing circuit in another application.
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www.ww.cooper.edu/courses/course-pages past-courses/EE151/MEMS-Ho1/ -20k -Cached (in GOOGLE).*
Book entitled “Nonvolatile Semiconductor Memory Technology”, Edited by William D. Brown and Joe. E. Brewer and published by IEEE Press (1998), ISBN 0-7803-1173-6, pp. 310-313, and pp. 363-398.
Article entitled “Applied Materials Introduces New Storage Capacitor Solution for Gigabit DRAMs” dated Jul. 8, 1998 from Applied Material Corporation web site.
Article entitled “Feature-Rich Flash Memories Deliver High Density” by Dave Bursky, Electronic Design, dated Aug. 9, 1999, vol. 47, No. 16.
Book entitled “Flash Memories”, Chapter 4 entitled “Physical Aspects of Cell operation and reliability” by Paolo Cappelletti et al. Kluwer Academic Publishers, 1999, pp. 157-160.
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Book entitled “Flash Memories” by Paolo Cappelletti et al. Kluwer Academic Publishers, 1999, Chapter 6, pp. 363-375.
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Book entitled “CMOS Membory Circuits” by Tegze P. Haraszti, Kluwer Academic Publishers, 2000, pp. 105-109.
Elms Richard
Grail Semiconductor
Silicon Valley Patent & Group LLP
Smith Brad
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