Amplifiers – Signal feedback – Combined with control of bias voltage of signal amplifier
Reexamination Certificate
2002-01-18
2003-12-30
Tokar, Michael (Department: 2819)
Amplifiers
Signal feedback
Combined with control of bias voltage of signal amplifier
C330S252000, C330S295000, C327S562000, C327S563000
Reexamination Certificate
active
06670847
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to an inductive amplifier. More specifically, the present invention relates to an inductive amplifier having a feed-forward boost function.
DESCRIPTION OF RELATED ART
FIG. 1
is a circuit diagram of a conventional inductive amplifier
100
, which may operate as an analog front end in a semiconductor chip. Inductive amplifier
100
includes inductors L
1
-L
2
, resistances rr
1
-rr
2
, capacitors C
1
-C
2
, resistors R
1
-R
2
, n-channel transistors N
1
-N
2
, current source I
1
, and output nodes O
N
and O
P
. A differential input signal VI
N
-VI
P
is applied to the gates of transistors N
1
and N
2
, respectively. The VI
N
and VI
P
signals represent the negative and positive phases of the differential input signal, respectively. As described below, inductive amplifier
100
operates to create boosted output signals VO
P
and VO
N
in response to the input signals VI
N
and VI
P
.
When the VI
N
input signal is high relative to the VI
P
input signal, then the VO
p
output voltage on node O
P
is pulled lower than the VO
N
output voltage on node O
N
. Conversely, when the VI
P
input signal is high relative to the VI
N
input signal, then the VO
N
output voltage on node O
N
is pulled lower than the VO
P
output voltage on node O
P
. The various elements of inductive amplifier
100
are connected such that the VO
P
and VO
N
output voltages are amplified with respect to the VI
P
and VI
N
input voltages.
FIG. 2
is a Bode plot illustrating several typical frequency response curves
201
-
203
for inductive amplifier
100
. The frequency response depends on the values of resistors R
1
, R
2
, rr
1
and rr
2
versus the values of inductors L
1
and L
2
. In the following description of
FIG. 2
, resistances rr
1
and rr
2
are considered to be the parasitic resistances of the inductors L
1
and L
2
on chip. Thus, curves
201
,
202
and
203
may represent the frequency response of inductive amplifier
100
when resistors R
1
and R
2
have resistances of 50, 100 and 300 Ohms, respectively. Note that for curve
201
, amplifier
100
exhibits an acceptable gain at frequencies below the 3 db roll-off frequency. However, for frequencies above the 3 db roll-off frequency of curve
201
, the gain is too low to enable inductive amplifier
100
to operate properly. Consequently, it may not be possible to use inductive amplifier
100
in communication applications that use high frequencies in the range of 5 GHz or greater.
Also note that as the values of resistors R
1
and R
2
decrease (i.e., curves
202
and
203
), amplifier
100
can exhibit peaking. This inherently reduces the maximum gain of amplifier
100
, because this amplifier must be designed within a limited range of resistances R
1
and R
2
.
It would therefore be desirable to have an improved inductive amplifier that exhibits a high gain at relatively high frequencies in the range of 1 GHz or greater.
SUMMARY
Accordingly, the present invention provides a low noise inductive amplifier having a feed-forward boost circuit that boosts the gain of an inductive amplifier circuit at high frequencies. That is, the feed-forward boost path provides an inductive amplifier having an increased bandwidth with respect to conventional amplifiers. In one embodiment, the feed-forward boost circuit adequately boosts the gain of the inductive amplifier to acceptable levels at frequencies greater than 1 GHz. For example, the feed-forward boost circuit can boost the gain of the inductive amplifier to enable operation at 10 Gigabits/second (Gb/sec).
In one embodiment, the feed-forward boost circuit includes a first boost transistor coupled receive a first differential input signal, a second boost transistor coupled to receive a second differential input signal, and a boost current source coupled to sources of both the first and second boost transistors. The drains of the first and second boost transistors are coupled to first and second intermediate output nodes of an inductive amplifier circuit, respectively. In one embodiment, the first and second intermediate output nodes correspond with ends of the load resistors of the inductive amplifier.
The AC current inserted by the feed-forward boost circuit causes the inductive amplifier to exhibit a relatively constant gain from DC (0 Hz) up to the resonant frequency of the entire LC tank circuit formed by the inductive amplifier circuit and the feed-forward boost circuit. Thus, the feed-forward boost circuit extends the range of frequencies at which the inductive amplifier exhibits an acceptable gain. Moreover, by controlling the sizing of the first and second boost transistors and the boost AC current source, the gain amplitude at the resonant frequency can be controlled. Moreover, it is possible to turn off the boost gain provided by feed-forward boost circuit by disabling the boost current source.
Advantageously, it is not necessary to use a negative resistance concept to achieve these results.
The inductive amplifier of the present invention can be used in any product that incorporates multi-gigabit transceivers that operate in the range of 1 Gb/sec and above. For example, the inductive amplifier of the present invention can be used in input sections of receivers in multi-gigabit transceivers, in field programmable gate arrays (FPGAs), or as stand alone parts.
In another embodiment, a loop-back path is provided, such that a signal provided by a transmitter is routed to the output terminals of the inductive amplifier, while the inductive amplifier is disabled. By providing this loop-back path, the transmitted signal can be routed to a bit-error rate monitor, such that bit-error rate of the transmitted signal can be accurately determined. The loop-back path therefore enables the inductive amplifier to be used in serializer/deserializer (SerDes) applications.
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patent: 4695806 (1987-09-01), Barrett
patent: 5521545 (1996-05-01), Terry et al.
patent: 5914637 (1999-06-01), Kagawa
patent: 6057714 (2000-05-01), Andrys et al.
patent: 6201443 (2001-03-01), Tanji
patent: 6392486 (2002-05-01), Lemay, Jr.
patent: 6404263 (2002-06-01), Wang
patent: 6429721 (2002-08-01), Armitage et al.
patent: 6446093 (2002-09-01), Tabuchi
patent: 2001/0018334 (2001-08-01), Ipek et al.
Hoffman E. Eric
Nguyen Khai
Tokar Michael
Xilinx , Inc.
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