Active solid-state devices (e.g. – transistors – solid-state diode – Integrated circuit structure with electrically isolated... – Passive components in ics
Reexamination Certificate
2000-12-14
2002-10-08
Nelms, David (Department: 2818)
Active solid-state devices (e.g., transistors, solid-state diode
Integrated circuit structure with electrically isolated...
Passive components in ics
C438S381000
Reexamination Certificate
active
06462396
ABSTRACT:
TECHNICAL FIELD
The present invention relates to the field of integrated circuits, and more specifically to an inductance formed above a semiconductor substrate.
BACKGROUND OF THE INVENTION
FIG. 1
shows an inductance
1
, including a number of turns or spirals, formed by a conductive element deposited on an insulating layer
2
. Insulating layer
2
, for example silicon oxide, rests on a semiconductor substrate
3
, generally made of silicon, which is connected to ground by its lower surface
4
in the example shown.
A strong disadvantage of the inductance of
FIG. 1
is that it has high losses. Thus, there exists a capacitance C with respect to the substrate, insulating layer
2
behaving as a dielectric. Further, substrate
3
is resistive and it exhibits a resistance R between its upper and lower surfaces
5
and
4
. Thus, when a variable current flows in inductance
1
, losses occur due to capacitance C and resistance R. These losses have the disadvantage of strongly decreasing quality factor Q of the inductance.
To overcome this disadvantage, European patent application EP-A-0780853 provides an inductance structure on a silicon substrate including a conductive plane located between the inductance and the substrate. This conductive plane, insulated from the substrate and the inductance, is connected to ground or to a cold point of the circuit, to establish an “electromagnetic shield or screen” between the inductance and the semiconductor substrate. To avoid dissipation by the creation of eddy currents in the conductive plane, said application provides dividing up the conductive plane.
A type of inductance with a divided inductive plane according to an example of the above-mentioned application is illustrated in FIG.
2
.
FIG. 2
illustrates an inductance
1
, an insulating layer
2
, and a substrate
3
having an upper surface
5
and a lower surface
4
connected to ground.
FIG. 2
also illustrates, above insulating layer
2
, a conductive plane
10
. Conductive plane
10
is divided in longitudinal strips
12
connected to a lateral strip
13
perpendicular to strips
12
and having, at its middle, a node
11
connected to ground. The effect of eddy currents is thus strongly decreased, but the structure of
FIG. 2
has disadvantages.
Thus, in
FIG. 2
, when inductance
1
is run through by a variable current, an electromotive force e due to the inductive coupling existing between strips
12
and the inductance appears in each of said strips. Similarly, an electromotive force e′ due to the inductive coupling between strip
13
and inductance
1
appears in lateral strip
13
. These electromotive forces cause losses. Indeed, each of the points of strips
12
and
13
is at a nonzero potential with respect to ground, due to induced electromagnetic forces, and, thereby, losses occur via a capacitance due to layer
2
used as a dielectric and the ohmic resistance of the substrate, these capacitance and ohmic resistance being distributed magnitudes, different at each point of the conductive plane.
All these losses make the behavior of the structure of
FIG. 2
unsatisfactory and decrease quality factor Q of the inductance.
The above-mentioned patent application provides other ways of dividing the conductive plane (see
FIGS. 7
,
9
, and
12
of this application). However, in all the provided examples of said application, including in its preferred embodiment corresponding to
FIG. 7
, there remain conductive plane portions in which a high induced electromotive force causes the undesirable effect that has been described.
SUMMARY OF THE INVENTION
Therefore, an object of the present invention is to provide an inductance structure arranged on a semiconductor substrate that does not have the above-described disadvantages.
Another object of the present invention is to provide an inductance structure arranged on a semiconductor substrate that minimizes losses due to the inductance operation.
Another object of the present invention is to provide an inductance structure that minimizes the electromotive forces induced in the conductive plane.
To achieve these objects as well as others, one embodiment of the present invention provides an inductance structure arranged on a semiconductor substrate, including an inductance and a conductive plane arranged between the inductance and the substrate. The conductive plane includes several separate conductive elements and several conductive tracks, each conductive track connecting at least one conductive element to a contact point M of the conductive plane. Each of the conductive tracks is arranged so that the resultant of the electromotive forces induced therein by said inductance is substantially null.
According to an embodiment of the present invention, each of the conductive tracks substantially follows an axis of symmetry of the inductance.
According to an embodiment of the present invention, the inductance substantially has the shape of a square and the conductive tracks are arranged along the diagonal and median lines of said square.
According to an embodiment of the present invention, the inductance substantially has the shape of a circle and the conductive tracks are arranged along the radiuses of said circle.
According to an embodiment of the present invention, said conductive elements have an elongated shape and are arranged perpendicularly to a spiral portion under which they are laid.
According to an embodiment of the present invention, said conductive elements are arranged under the inductance spirals only.
REFERENCES:
patent: 5717243 (1998-02-01), Lowther
patent: 5936299 (1999-08-01), Burghartz et al.
patent: 6124624 (2000-09-01), Van Roosmalen et al.
patent: 6310387 (2001-10-01), Seefeldt et al.
patent: 0 780 853 (1997-06-01), None
patent: WO 98/50956 (1998-11-01), None
Hoang Quoc
Iannucci Robert
Jorgenson Lisa K.
Nelms David
Seed IP Law Group PLLC
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