Inductance mitigation through switching density analysis

Details Inductance mitigation through switching density analysis Inductance mitigation through switching density analysis

2007-04-04

2011-11-15

Dinh, Paul (Department: 2825)

Computer-aided design and analysis of circuits and semiconductor

Integrated circuit design processing

Logic design processing

C716S107000, C716S108000, C716S110000, C716S111000, C716S115000

Reexamination Certificate

active

08060846

ABSTRACT:
Embodiments of a method for detecting potential areas of inductive coupling in a high density integrated circuit design are described. The inductance mitigation process first converts the inductive analysis into a density problem. The density of wires within a region that may switch within a portion of the system clock are compared to the density of wires will not switch within that same time. Regions of the chip that have a high ratio of density of switching wires versus non-switching wires are determined to have the potential of an inductive coupling problem. Additional grounded metal is added into the problematic regions of the chip to improve the switching versus non-switching wire density.

REFERENCES:
patent: 2002/0104064 (2002-08-01), Sasaki et al.
patent: 2005/0120316 (2005-06-01), Suaya et al.

Affiliated with

Also associated with

Rating

Inductance mitigation through switching density analysis does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Inductance mitigation through switching density analysis, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Inductance mitigation through switching density analysis will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-4277121