Individualized low parasitic power distribution lines...

Details Individualized low parasitic power distribution lines... Individualized low parasitic power distribution lines...

2006-11-14

2006-11-14

Andujar, Leonardo (Department: 2826)

Active solid-state devices (e.g., transistors, solid-state diode

Lead frame

With structure for mounting semiconductor chip to lead frame

C257S672000, C257S781000, C257S784000, C257S691000

Reexamination Certificate

active

07135759

ABSTRACT:
An integrated circuit (IC) chip, mounted on a leadframe, has a network of power distribution lines deposited on the surface of the chip so that these lines are located over active components of the IC, connected vertically by metal-filled vias to selected active components below the lines, and also by conductors to segments of the leadframe. Furthermore, the lines are fabricated with a sheet resistance of less than 1.5 mΩ/□ and the majority of the lines is patterned as straight lines between the vias and the conductors, respectively.

REFERENCES:
patent: 5468993 (1995-11-01), Tani
patent: 5973554 (1999-10-01), Yamasaki et al.
Wolf et al., Silicon Processing for the VLSI Era, Lattice Press, vol. 1, pp. 857-858.

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