Individual data line strobe-offset control in memory systems

Details Individual data line strobe-offset control in memory systems Individual data line strobe-offset control in memory systems

2007-01-09

2010-02-23

Barbee, Manuel L (Department: 2857)

Data processing: measuring, calibrating, or testing

Calibration or correction system

Signal frequency or phase correction

C702S072000, C702S079000, C365S189070, C365S193000, C365S194000

Reexamination Certificate

active

07668679

ABSTRACT:
Systems and methods for strobe signal timing calibration and control in strobe-based memory systems are provided below. These strobe-offset control systems and methods receive a strobe signal from a memory device and in turn automatically generate separate per-bit strobe signals for use in receiving data on each data line of a memory system. The systems/methods generate the optimal per-bit strobe signals by automatically calibrating per-bit offset timing between data signals of individual data bits and corresponding strobe signals. The strobe-offset control system effectively removes the detected phase difference between the data signal and the strobe signal.

REFERENCES:
patent: 4410916 (1983-10-01), Pratt et al.
patent: 4687954 (1987-08-01), Yasuda
patent: 4926447 (1990-05-01), Corsetto et al.
patent: 5060239 (1991-10-01), Briscoe et al.
patent: 5334883 (1994-08-01), Rosenthal
patent: 5341371 (1994-08-01), Simpson
patent: 5655105 (1997-08-01), McLaury
patent: 5805619 (1998-09-01), Gardner et al.
patent: 5832303 (1998-11-01), Murase et al.
patent: 5935257 (1999-08-01), Nishimura
patent: 5978281 (1999-11-01), Anand et al.
patent: 6023174 (2000-02-01), Kirsch
patent: 6028816 (2000-02-01), Takemae et al.
patent: 6055587 (2000-04-01), Asami
patent: 6279073 (2001-08-01), McCracken
patent: 6316980 (2001-11-01), Vogt
patent: 6396887 (2002-05-01), Ware
patent: 6466491 (2002-10-01), Yanagawa
patent: 6498766 (2002-12-01), Lee
patent: 6512704 (2003-01-01), Wu et al.
patent: 6570800 (2003-05-01), Tanaka
patent: 6570944 (2003-05-01), Best
patent: 6643787 (2003-11-01), Zerbe
patent: 6646929 (2003-11-01), Moss
patent: 6646953 (2003-11-01), Stark
patent: 6675272 (2004-01-01), Ware
patent: 6691214 (2004-02-01), Li et al.
patent: 6707723 (2004-03-01), Jeong
patent: 6759881 (2004-07-01), Kizer et al.
patent: 6782459 (2004-08-01), Ware
patent: 6819157 (2004-11-01), Cao
patent: 6836503 (2004-12-01), Best
patent: 6836521 (2004-12-01), Ware
patent: 6930932 (2005-08-01), Rentschler
patent: 6940760 (2005-09-01), Borkenhagen et al.
patent: 6940768 (2005-09-01), Dahlberg
patent: 7031205 (2006-04-01), Han
patent: 2001/0020278 (2001-09-01), Saito
patent: 2002/0009004 (2002-01-01), Hamada et al.
patent: 2002/0149397 (2002-10-01), Dally et al.
patent: 2003/0065465 (2003-04-01), Johnson et al.
patent: 2003/0091136 (2003-05-01), Sugita
patent: 2003/0179611 (2003-09-01), Liou
patent: 2003/0221050 (2003-11-01), Hong et al.
patent: 2004/0044919 (2004-03-01), Dabral
patent: 2004/0084537 (2004-05-01), Best
patent: 2004/0213067 (2004-10-01), Best
patent: 2004/0230715 (2004-11-01), Huang
patent: 2005/0005056 (2005-01-01), Ware
patent: 2005/0071707 (2005-03-01), Hampel
patent: 2005/0110544 (2005-05-01), Suda et al.
patent: 2005/0141294 (2005-06-01), Bonelli
patent: 2005/0163203 (2005-07-01), Ware
patent: 19920335 (2000-09-01), None
patent: WO98/44674 (1998-10-01), None
patent: WO99/17183 (1999-04-01), None
International Preliminary Report on Patentability and Written Opinion of the International Searching Authority in International Application PCT/US2005/028709, European Patent Office, Mar. 1, 2007, 13 pages.
Altera, “Using Source-Synchronous Signaling with DPA in Stratix GX Devices,” Application Note 236, pp. 1-18, Altera Corporation, Jan. 2003, available at http://www.altera.com/literature/an/an236.pdf.
CMOS Parallel-to-Serial FIFO 256×16, 512×16, 1024×16, pp. 1-10, Integrated Device Technology Corporation, Dec. 1999, available at http://www.digchip.com/datasheets/parts/datasheet/222/IDT72105.php.
Collins, Hansel A. and Nikel, Ronald E., “DDR-SDRAM, high-speed, source-synchronous interfaces create design challenges”, EDN, Sep. 2, 1999, pp. 63, 64, 66, 68, 70, 72 available at http://wwww.ednmag/reg/1999/090299/18ms544.htm.
DDR-SDRAM-2: Detailed Specifications, FIND, Nov. 1998, pp. 1-14, vol. 16, No. 4.
DDR-SDRAM-4: DLL Circuit Technology, FIND, Nov. 1998, pp. 1-4, vol. 16, No. 4.
Horowitz, Hill: “The Art of Electronics” (second edition), 1989, Cambridge, p. 231-232.
IBM Corporation, “PowerPC Embedded Processors PowerPC 440GP-DDR SDRAM Controller Initialization”, Hopewell Junction,NY., Mar. 20, 2002, pp. 1-9.
Khatib, Jamil, “FIFO, First-In-First Out Memory,” pp. 1-6, Mar. 28, 1999, available at http://www.geocities.com/Silicon Valley/Pines/6639/ip/fifo.html.
Rajpal, Suneel, et al., “Designing with FIF0s,” Technical Note TN-06, pp. 1-2, Integrated Device Technology Coroporation, Nov. 1997, available at http://www.elektroniknet.de/fileadmin/user upload/IDT/TN-062020Designing20with20Async2OFIFOs.pdf.
Ryan, Kevin, “DDR SDRAM Functionality and Controller Read Data Capture”, Micron Technology, Inc. DesignLine, 1999, pp. 1-24, vol. 8, Issue available at www.micron.com/mti/msp/html/dlindex.html.
Schumann, T. and Klar, H., “An Asynchronous up/down Counter for Control of a Self-timed, Wave-pipelined Array Mutiplier,” Abstract, ACiD-WL Workshop, Groningen, the Netherlands, Sep. 1996, available at http://mikro.ee.tuberlin.de/forschung/sgemos/abstractACiD.ps.gz.
SN74ALVC7804 512×8 First-In, First-Out Memory, SCAS432, pp. 1-10 & Addendum pp. 1-3, Texas Instruments Corporation, Jan. 1995, available at http://focus.ti.com/lit/ds/symlink/sn74alvc7804.pdf.
Tech Brief 31: Using Delay Lines to Generate Multi-Phased Clocks, p. 1, Dallas Semiconductor Corporation, Dec. 12, 2001, available at http://www.maximic.com/appnotes.cfm/appnote—number/880.
XILINX, “Using the XC9500 Timing Model,” Application Note XAPP071, pp. 2-9 to 2-12, XILINX Corporation, Jan. 1997, available at http://direct.xilinx.com/bvdocs/appnotes/xapp071.pdf.
Ajanta Chakraborty: “Efficient Self-Timed Interfaces for Crossing Clock Domains,” thesis submitted to Department of Computer Science, University of British Columbia, Aug. 2003, 74 pgs.
Jens Muttersbach, Thomas Villiger, Worfgang Fichtner: “Practical Design of Globally-Asynchronous Locally-Synchronous Systems,” Sixth International Symposium on Advanced Research in Asynchronous Circuits and Systems (ASYNC 2000), 8 pgs.

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